[llvm] r229234 - R600/SI: Really fix size of VReg_1

[Matt Arsenault]

Author: arsenm
Date: Fri Feb 13 21:54:32 2015
New Revision: 229234

URL: http://llvm.org/viewvc/llvm-project?rev=229234&view=rev
Log:
R600/SI: Really fix size of VReg_1

Modified:
    llvm/trunk/lib/Target/R600/SIRegisterInfo.td

Modified: llvm/trunk/lib/Target/R600/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIRegisterInfo.td?rev=229234&r1=229233&r2=229234&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIRegisterInfo.td Fri Feb 13 21:54:32 2015
@@ -209,7 +209,9 @@ def VReg_256 : RegisterClass<"AMDGPU", [
 
 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
 
-def VReg_1 : RegisterClass<"AMDGPU", [i1, i32], 32, (add VGPR_32)>;
+def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
+  let Size = 32;
+}
 
 class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> {
   let OperandNamespace = "AMDGPU";