[PATCH] [X86][SSE] psrl(w/d/q) and psll(w/d/q) bit shifts for SSE2

[Quentin Colombet]

Hi Simon,

Chandler did all the work of the review so I’ll leave it the final LGTM.
Here are my comments.

Thanks for your patience.
-Quentin


REPOSITORY
  rL LLVM

================
Comment at: test/CodeGen/X86/vec_insert-5.ll:68
@@ -67,3 +67,3 @@
 ; CHECK-NEXT:    retl
-  %s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
+  %s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
   ret <16 x i8> %s
----------------
I guess you modified the input IR to have additional coverage.
If that is the case, I believe a new test case with that input would be preferable, i.e., having both tests.

================
Comment at: test/CodeGen/X86/vec_insert-5.ll:77
@@ -76,3 +76,3 @@
 ; CHECK-NEXT:    retl
-  %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 7, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 14, i32 undef, i32 undef>
   ret <16 x i8> %s
----------------
Same here.

http://reviews.llvm.org/D6649

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