[PATCH] Add saving and restoring of r30 to the prologue and epilogue, respectively
Justin Hibbits
jrh29 at alumni.cwru.edu
Wed Jan 7 22:21:59 PST 2015
Hi hfinkel,
The PIC additions didn't update the prologue and epilogue code to save and restore r30 (PIC base register). This does that.
REPOSITORY
rL LLVM
http://reviews.llvm.org/D6876
Files:
lib/Target/PowerPC/PPCFrameLowering.cpp
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
test/CodeGen/PowerPC/ppc32-pic-large.ll
test/CodeGen/PowerPC/ppc32-pic.ll
Index: lib/Target/PowerPC/PPCFrameLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCFrameLowering.cpp
+++ lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -644,6 +644,13 @@
.addImm(FPOffset)
.addReg(SPReg);
+ if (isPIC && !isDarwinABI && !isPPC64 && MF.getInfo<PPCFunctionInfo>()->usesPICBase())
+ // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
+ BuildMI(MBB, MBBI, dl, StoreInst)
+ .addReg(PPC::R30)
+ .addImm(-8U)
+ .addReg(SPReg);
+
if (HasBP)
// FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
BuildMI(MBB, MBBI, dl, StoreInst)
@@ -1003,6 +1010,13 @@
.addImm(FPOffset)
.addReg(SPReg);
+ if (isPIC && !isDarwinABI && !isPPC64 && MF.getInfo<PPCFunctionInfo>()->usesPICBase())
+ // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
+ BuildMI(MBB, MBBI, dl, LoadInst)
+ .addReg(PPC::R30)
+ .addImm(-8U)
+ .addReg(SPReg);
+
if (HasBP)
BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
.addImm(BPOffset)
Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -307,6 +307,7 @@
if (M->getPICLevel() == PICLevel::Small) {
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
+ MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
} else {
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
Index: test/CodeGen/PowerPC/ppc32-pic-large.ll
===================================================================
--- test/CodeGen/PowerPC/ppc32-pic-large.ll
+++ test/CodeGen/PowerPC/ppc32-pic-large.ll
@@ -12,6 +12,7 @@
; LARGE-BSS: [[POFF:\.L[0-9]+\$poff]]:
; LARGE-BSS-NEXT: .long .LTOC-[[PB:\.L[0-9]+\$pb]]
; LARGE-BSS-NEXT: foo:
+; LARGE-BSS: stw 30, -8(1)
; LARGE-BSS: bl [[PB]]
; LARGE-BSS-NEXT: [[PB]]:
; LARGE-BSS: mflr 30
@@ -19,5 +20,6 @@
; LARGE-BSS-NEXT: add 30, [[REG]], 30
; LARGE-BSS: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
; LARGE-BSS: lwz {{[0-9]+}}, 0([[VREG]])
+; LARGE-BSS: lwz 30, -8(1)
; LARGE-BSS: [[VREF]]:
; LARGE-BSS-NEXT: .long bar
Index: test/CodeGen/PowerPC/ppc32-pic.ll
===================================================================
--- test/CodeGen/PowerPC/ppc32-pic.ll
+++ test/CodeGen/PowerPC/ppc32-pic.ll
@@ -10,7 +10,9 @@
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"PIC Level", i32 1}
; SMALL-BSS-LABEL:foo:
+; SMALL-BSS: stw 30, -8(1)
; SMALL-BSS: bl _GLOBAL_OFFSET_TABLE_ at local-4
; SMALL-BSS: mflr 30
; SMALL-BSS: lwz [[VREG:[0-9]+]], bar at GOT(30)
; SMALL-BSS: lwz {{[0-9]+}}, 0([[VREG]])
+; SMALL-BSS: lwz 30, -8(1)
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