[llvm] r223774 - [x86] Fix the test to actually test things for the CPU names, add the
Steven Wu
stevenwu at apple.com
Fri Dec 19 17:06:25 PST 2014
> On Dec 19, 2014, at 4:35 PM, Chandler Carruth <chandlerc at gmail.com> wrote:
>
> On Fri, Dec 19, 2014 at 3:27 PM, Steven Wu <stevenwu at apple.com <mailto:stevenwu at apple.com>> wrote:
> Hi Chandler
>
> The testcases you committed is breaking our internal bots running with gmalloc. When gmalloc is enable, it will print version numbers and etc. to stderr.
> Here is an example:
> GuardMalloc[llc-23060]: Allocations will be placed on 16 byte boundaries.
> GuardMalloc[llc-23060]: - Some buffer overruns may not be noticed.
> GuardMalloc[llc-23060]: - Applications using vector instructions (e.g., SSE) should work.
> GuardMalloc[llc-23060]: version 104
>
> Can you modify the testcase so that it won’t be triggered by gmalloc (like grep for error?)
>
> I would much rather not.
>
> I don't know why it is reasonable to support arbitrary output to stderr in test cases. Lots of our test cases examine stderr for specific output... Why do those work?
It is not arbitrary output to stderr. Gmalloc only prints the 4 lines above (in the very beginning of stderr) when it is happy.
All our existing tests don’t care about 4 extra lines in the beginning of stderr and all the other count commands in the tests are following a grep command.
Gmalloc has found few problems in the past so I don’t want to kill the gmalloc if your testcase can be written in other way.
Thanks
Steven
>
>
> Thanks
>
> Steven
>
> > On Dec 9, 2014, at 6:25 AM, Chandler Carruth <chandlerc at gmail.com <mailto:chandlerc at gmail.com>> wrote:
> >
> > Author: chandlerc
> > Date: Tue Dec 9 08:25:55 2014
> > New Revision: 223774
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=223774&view=rev <http://llvm.org/viewvc/llvm-project?rev=223774&view=rev>
> > Log:
> > [x86] Fix the test to actually test things for the CPU names, add the
> > missing barcelona CPU which that test uncovered, and remove the 32-bit
> > x86 CPUs which I really wasn't prepared to audit and test thoroughly.
> >
> > If anyone wants to clean up the 32-bit only x86 CPUs, go for it.
> >
> > Also, if anyone else wants to try to de-duplicate the AMD CPUs, that'd
> > be cool, but from the looks of it wouldn't save as much as it did for
> > the Intel CPUs.
> >
> > Modified:
> > llvm/trunk/lib/Target/X86/X86.td
> > llvm/trunk/test/CodeGen/X86/cpus.ll
> >
> > Modified: llvm/trunk/lib/Target/X86/X86.td
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=223774&r1=223773&r2=223774&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=223774&r1=223773&r2=223774&view=diff>
> > ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86.td (original)
> > +++ llvm/trunk/lib/Target/X86/X86.td Tue Dec 9 08:25:55 2014
> > @@ -433,6 +433,10 @@ def : Proc<"amdfam10", [FeatureSS
> > Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
> > FeaturePOPCNT, FeatureSlowBTMem,
> > FeatureSlowSHLD]>;
> > +def : Proc<"barcelona", [FeatureSSE4A,
> > + Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
> > + FeaturePOPCNT, FeatureSlowBTMem,
> > + FeatureSlowSHLD]>;
> > // Bobcat
> > def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
> > FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
> >
> > Modified: llvm/trunk/test/CodeGen/X86/cpus.ll
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cpus.ll?rev=223774&r1=223773&r2=223774&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cpus.ll?rev=223774&r1=223773&r2=223774&view=diff>
> > ==============================================================================
> > --- llvm/trunk/test/CodeGen/X86/cpus.ll (original)
> > +++ llvm/trunk/test/CodeGen/X86/cpus.ll Tue Dec 9 08:25:55 2014
> > @@ -1,32 +1,28 @@
> > -; RUN: llc < %s -o /dev/null -mcpu=prescott
> > -; RUN: llc < %s -o /dev/null -mcpu=nocona
> > -; RUN: llc < %s -o /dev/null -mcpu=core2
> > -; RUN: llc < %s -o /dev/null -mcpu=penryn
> > -; RUN: llc < %s -o /dev/null -mcpu=nehalem
> > -; RUN: llc < %s -o /dev/null -mcpu=westmere
> > -; RUN: llc < %s -o /dev/null -mcpu=sandybridge
> > -; RUN: llc < %s -o /dev/null -mcpu=ivybridge
> > -; RUN: llc < %s -o /dev/null -mcpu=haswell
> > -; RUN: llc < %s -o /dev/null -mcpu=broadwell
> > -; RUN: llc < %s -o /dev/null -mcpu=bonnell
> > -; RUN: llc < %s -o /dev/null -mcpu=silvermont
> > -; RUN: llc < %s -o /dev/null -mcpu=k8
> > -; RUN: llc < %s -o /dev/null -mcpu=opteron
> > -; RUN: llc < %s -o /dev/null -mcpu=athlon64
> > -; RUN: llc < %s -o /dev/null -mcpu=athlon-fx
> > -; RUN: llc < %s -o /dev/null -mcpu=k8-sse3
> > -; RUN: llc < %s -o /dev/null -mcpu=opteron-sse3
> > -; RUN: llc < %s -o /dev/null -mcpu=athlon64-sse3
> > -; RUN: llc < %s -o /dev/null -mcpu=amdfam10
> > -; RUN: llc < %s -o /dev/null -mcpu=barcelona
> > -; RUN: llc < %s -o /dev/null -mcpu=bdver1
> > -; RUN: llc < %s -o /dev/null -mcpu=bdver2
> > -; RUN: llc < %s -o /dev/null -mcpu=bdver3
> > -; RUN: llc < %s -o /dev/null -mcpu=bdver4
> > -; RUN: llc < %s -o /dev/null -mcpu=btver1
> > -; RUN: llc < %s -o /dev/null -mcpu=btver2
> > -; RUN: llc < %s -o /dev/null -mcpu=winchip-c6
> > -; RUN: llc < %s -o /dev/null -mcpu=winchip2
> > -; RUN: llc < %s -o /dev/null -mcpu=c3
> > -; RUN: llc < %s -o /dev/null -mcpu=c3-2
> > -; RUN: llc < %s -o /dev/null -mcpu=geode
> > +; Test that the CPU names work.
> > +;
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=penryn 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nehalem 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=westmere 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sandybridge 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=ivybridge 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=haswell 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=broadwell 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bonnell 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=silvermont 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k8 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=opteron 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon64 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-fx 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k8-sse3 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=opteron-sse3 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon64-sse3 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=amdfam10 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=barcelona 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver1 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver2 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver3 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver4 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver1 2>&1 | count 0
> > +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver2 2>&1 | count 0
> >
> >
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