[llvm] r223667 - [Hexagon] Adding combine reg, reg with predicated forms.

[Colin LeMahieu]

Author: colinl
Date: Mon Dec  8 11:33:06 2014
New Revision: 223667

URL: http://llvm.org/viewvc/llvm-project?rev=223667&view=rev
Log:
[Hexagon] Adding combine reg, reg with predicated forms.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
    llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt
    llvm/trunk/test/MC/Disassembler/Hexagon/alu32_pred.txt

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=223667&r1=223666&r2=223667&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Mon Dec  8 11:33:06 2014
@@ -208,6 +208,13 @@ def: BinOp32_pat<xor, A2_xor, i32>;
 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
     isCodeGenOnly = 0 in {
   def S2_packhl    : T_ALU32_3op  <"packhl",  0b101, 0b100, 0, 0>;
+
+  let isPredicable = 1 in
+    def A2_combinew  : T_ALU32_3op  <"combine", 0b101, 0b000, 0, 0>;
+
+  // Conditional combinew uses "newt/f" instead of "t/fnew".
+  def C2_ccombinewt    : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
+  def C2_ccombinewf    : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
 }
 
 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg"  in

Modified: llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt?rev=223667&r1=223666&r2=223667&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt Mon Dec  8 11:33:06 2014
@@ -10,6 +10,8 @@
 # CHECK: r17 = combine(r31.l, r21.l)
 0xb0 0xe2 0x0f 0x7c
 # CHECK: r17:16 = combine(#21, #31)
+0x10 0xdf 0x15 0xf5
+# CHECK: r17:16 = combine(r21, r31)
 0xf1 0xc3 0x75 0x73
 # CHECK: r17 = mux(p3, r21, #31)
 0xb1 0xc2 0xff 0x73

Modified: llvm/trunk/test/MC/Disassembler/Hexagon/alu32_pred.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/alu32_pred.txt?rev=223667&r1=223666&r2=223667&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/alu32_pred.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/alu32_pred.txt Mon Dec  8 11:33:06 2014
@@ -6,6 +6,10 @@
 # CHECK: if (p3) r17 = aslh(r21)
 0x11 0xe3 0x35 0x70
 # CHECK: if (p3) r17 = asrh(r21)
+0x70 0xdf 0x15 0xfd
+# CHECK: if (p3) r17:16 = combine(r21, r31)
+0xf0 0xdf 0x15 0xfd
+# CHECK: if (!p3) r17:16 = combine(r21, r31)
 0x71 0xdf 0x15 0xf9
 # CHECK: if (p3) r17 = and(r21, r31)
 0x71 0xdf 0x35 0xf9