[PATCH] Masked Vector Load/Store Intrinsics

[Demikhovsky, Elena]

Brief description:
1) Store
call void @llvm.masked.store.v16i32(i8* %addr, <16 x i32>%val, i32 4, <16 x i1>%mask)

store vector value %val under %addr, write only lanes where an appropriate %mask bit is on.
Number of elements in %mask and in %val should be the same.

2) Load
%res = call <16 x float> @llvm.masked.load.v16f32(i8* %addr, <16 x float>%src0, i32 4, <16 x i1>%mask)

load vector value from %addr, read only lanes where an appropriate %mask bit is on.
Number of elements in %mask and in %res and in %src0 should be the same.

Fill masked-off lanes with elements from %src0 (like “select”).

In the both cases don’t access memory under masked-off lanes.
Supported types depend on target.
Load/store mean consecutive access. I plan add intrinsics for the strided and random access in the future.

-           Elena

From: mankeyrabbit at gmail.com [mailto:mankeyrabbit at gmail.com] On Behalf Of James Molloy
Sent: Monday, November 10, 2014 15:28
To: reviews+D6191+public+d24d75579f47f6d4 at reviews.llvm.org
Cc: Demikhovsky, Elena; Adam Nemet; Hal Finkel; rob.khasanov at gmail.com; Owen Anderson; LLVM Commits; nurmukhametov.alex at gmail.com
Subject: Re: [PATCH] Masked Vector Load/Store Intrinsics

Hi Elena,

There doesn't seem to be a change to LangRef here. Could you please briefly describe the semantics of masked load and store intrinsics?

We have strided load/store instructions in NEON that could be modelled with them, depending on their semantics.

Cheers,

James

On 10 November 2014 13:19, Elena Demikhovsky <elena.demikhovsky at intel.com<mailto:elena.demikhovsky at intel.com>> wrote:
Hi anemet, hfinkel, rob.khasanov, resistor,

Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores.
Added SDNodes for masked operations and lowering patterns for X86 code generator.

Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.

http://reviews.llvm.org/D6191

Files:
  include/llvm/Analysis/TargetTransformInfo.h
  include/llvm/CodeGen/ISDOpcodes.h
  include/llvm/CodeGen/SelectionDAG.h
  include/llvm/CodeGen/SelectionDAGNodes.h
  include/llvm/IR/IRBuilder.h
  include/llvm/IR/Intrinsics.h
  include/llvm/IR/Intrinsics.td
  include/llvm/Target/TargetSelectionDAG.td
  lib/Analysis/TargetTransformInfo.cpp
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  lib/CodeGen/SelectionDAG/LegalizeTypes.h
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
  lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  lib/IR/Function.cpp
  lib/IR/IRBuilder.cpp
  lib/IR/Verifier.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86InstrAVX512.td
  lib/Target/X86/X86InstrSSE.td
  lib/Target/X86/X86TargetTransformInfo.cpp
  lib/Transforms/Vectorize/LoopVectorize.cpp
  test/CodeGen/X86/masked_memop.ll
  test/Transforms/LoopVectorize/X86/mask1.ll
  test/Transforms/LoopVectorize/X86/mask2.ll
  test/Transforms/LoopVectorize/X86/mask3.ll
  test/Transforms/LoopVectorize/X86/mask4.ll
  utils/TableGen/CodeGenTarget.cpp
  utils/TableGen/IntrinsicEmitter.cpp

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