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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Brief description:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">1) Store<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">call void @llvm.masked.store.v16i32(i8* %addr, <16 x i32>%val, i32 4, <16 x i1>%mask)<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">store vector value %val under %addr, write only lanes where an appropriate %mask bit is on.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Number of elements in %mask and in %val should be the same.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">2) Load<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">%res = call <16 x float> @llvm.masked.load.v16f32(i8* %addr, <16 x float>%src0, i32 4, <16 x i1>%mask)<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">load vector value from %addr, read only lanes where an appropriate %mask bit is on.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Number of elements in %mask and in %res and in %src0 should be the same.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Fill masked-off lanes with elements from %src0 (like “select”).<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">In the both cases don’t access memory under masked-off lanes.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Supported types depend on target.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Load/store mean consecutive access. I plan add intrinsics for the strided and random access in the future.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo1">
<![if !supportLists]><span style="font-family:"Calibri","sans-serif";color:#31849B"><span style="mso-list:Ignore">-<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]><span dir="LTR"></span><b><i><span style="color:#31849B"> Elena<o:p></o:p></span></i></b></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> mankeyrabbit@gmail.com [mailto:mankeyrabbit@gmail.com]
<b>On Behalf Of </b>James Molloy<br>
<b>Sent:</b> Monday, November 10, 2014 15:28<br>
<b>To:</b> reviews+D6191+public+d24d75579f47f6d4@reviews.llvm.org<br>
<b>Cc:</b> Demikhovsky, Elena; Adam Nemet; Hal Finkel; rob.khasanov@gmail.com; Owen Anderson; LLVM Commits; nurmukhametov.alex@gmail.com<br>
<b>Subject:</b> Re: [PATCH] Masked Vector Load/Store Intrinsics<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hi Elena,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">There doesn't seem to be a change to LangRef here. Could you please briefly describe the semantics of masked load and store intrinsics?<o:p></o:p></p>
</div>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">We have strided load/store instructions in NEON that could be modelled with them, depending on their semantics.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<div>
<p class="MsoNormal">Cheers,<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
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<div>
<p class="MsoNormal">James<o:p></o:p></p>
</div>
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<div>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On 10 November 2014 13:19, Elena Demikhovsky <<a href="mailto:elena.demikhovsky@intel.com" target="_blank">elena.demikhovsky@intel.com</a>> wrote:<o:p></o:p></p>
<p class="MsoNormal" style="margin-bottom:12.0pt">Hi anemet, hfinkel, rob.khasanov, resistor,<br>
<br>
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer
asks the target about availability of masked vector loads and stores.<br>
Added SDNodes for masked operations and lowering patterns for X86 code generator.<br>
<br>
Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.<br>
<br>
<a href="http://reviews.llvm.org/D6191" target="_blank">http://reviews.llvm.org/D6191</a><br>
<br>
Files:<br>
include/llvm/Analysis/TargetTransformInfo.h<br>
include/llvm/CodeGen/ISDOpcodes.h<br>
include/llvm/CodeGen/SelectionDAG.h<br>
include/llvm/CodeGen/SelectionDAGNodes.h<br>
include/llvm/IR/IRBuilder.h<br>
include/llvm/IR/Intrinsics.h<br>
include/llvm/IR/Intrinsics.td<br>
include/llvm/Target/TargetSelectionDAG.td<br>
lib/Analysis/TargetTransformInfo.cpp<br>
lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
lib/CodeGen/SelectionDAG/LegalizeTypes.h<br>
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h<br>
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp<br>
lib/IR/Function.cpp<br>
lib/IR/IRBuilder.cpp<br>
lib/IR/Verifier.cpp<br>
lib/Target/X86/X86ISelLowering.cpp<br>
lib/Target/X86/X86InstrAVX512.td<br>
lib/Target/X86/X86InstrSSE.td<br>
lib/Target/X86/X86TargetTransformInfo.cpp<br>
lib/Transforms/Vectorize/LoopVectorize.cpp<br>
test/CodeGen/X86/masked_memop.ll<br>
test/Transforms/LoopVectorize/X86/mask1.ll<br>
test/Transforms/LoopVectorize/X86/mask2.ll<br>
test/Transforms/LoopVectorize/X86/mask3.ll<br>
test/Transforms/LoopVectorize/X86/mask4.ll<br>
utils/TableGen/CodeGenTarget.cpp<br>
utils/TableGen/IntrinsicEmitter.cpp<br>
<br>
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<p class="MsoNormal"><o:p> </o:p></p>
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