[PATCH] [mips] Enable code generation for the MIPS II target.

[Daniel Sanders]

LGTM with some test corrections and a nit. Also, please reword the title line of the commit message. At the moment it implies that MIPS-II will work after that patch and that isn't quite true yet.

I understand you're testing with a qemu that has been patched to have a MIPS-II CPU definition. Are you planning to upstream that patch to qemu.org?

================
Comment at: lib/Target/Mips/MipsSubtarget.cpp:132-134
@@ -130,3 +131,5 @@
+
+  // Don't even attempt to generate code for MIPS-I, MIPS-III, and
   // MIPS-V. They have not been tested and currently exist for the integrated
   // assembler only.
   if (MipsArchVersion == Mips1)
----------------
Nit: Line wrapping

================
Comment at: test/CodeGen/Mips/llvm-ir/mul.ll:101
@@ +100,3 @@
+  ; M2:         mult    $5, $6
+  ; M2:         mflo    $2
+  ; M2:         multu   $5, $7
----------------
This result register isn't guaranteed to be $2. It ought to be checked with a variable.

================
Comment at: test/CodeGen/Mips/llvm-ir/mul.ll:105
@@ +104,3 @@
+  ; M2:         mfhi    $4
+  ; M2:         addu    $2, $4, $2
+  ; M2:         addu    $2, $2, $[[T0]]
----------------
This result register isn't guaranteed to be $2. It ought to be checked with a variable.

================
Comment at: test/CodeGen/Mips/llvm-ir/mul.ll:111-112
@@ +110,4 @@
+  ; 32R1-R2:    mfhi    $[[T0:[0-9]+]]
+  ; 32R1-R2:    mul     $2, $4, $7
+  ; 32R1-R2:    mul     $4, $5, $6
+  ; 32R1-R2:    addu    $[[T0]], $[[T0]], $4
----------------
These result registers aren't guaranteed to be $2 and $4 respectively. They ought to be checked with a variable.

================
Comment at: test/CodeGen/Mips/llvm-ir/mul.ll:117
@@ +116,3 @@
+  ; 32R6:       mul     $[[T0:[0-9]+]], $5, $6
+  ; 32R6:       muhu    $2, $5, $7
+  ; 32R6:       addu    $[[T0]], $2, $[[T0]]
----------------
This result register isn't guaranteed to be $2. It ought to be checked with a variable.

================
Comment at: test/CodeGen/Mips/llvm-ir/mul.ll:119
@@ +118,3 @@
+  ; 32R6:       addu    $[[T0]], $2, $[[T0]]
+  ; 32R6:       mul     $2, $4, $7
+  ; 32R6:       addu    $2, $[[T0]], $2
----------------
This result register isn't guaranteed to be $2. It ought to be checked with a variable.

http://reviews.llvm.org/D6150