[PATCH] [AArch64] Load Balancing for AES instructions on Cortex-A57

[Renato Golin]

The code looks ok, but I'm not sure about the architecture decisions. I'd rather Tim or James had a look.

cheers,
--renato

================
Comment at: lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp:566
@@ -553,1 +565,3 @@
+      bool isAES = isAESEnDe(I) || isAESMix(I);
+      Change = Change || isAES;
       if (G->requiresFixup() && &*I == G->getLast())
----------------
You could have moved isAES up and made Change one line

================
Comment at: test/CodeGen/AArch64/aes-load-balancing.ll:14
@@ +13,3 @@
+;CHECK-LABEL: aes_load_balancing:
+;CHECK: aese v0.16b, v{{[0-9]}}.16b
+;CHECK: aesmc v0.16b, v0.16b
----------------
can you use CHECK variables here? Like:

    ;CHECK: aese v[[accum:0-9]].16b, ...

http://reviews.llvm.org/D6154