[PATCH] [AArch64] Load Balancing for AES instructions on Cortex-A57

[Z. Zheng]

Hi jmolloy, t.p.northover, apazos, mcrosier,

On Cortex-A57, an AES chain achieves best performance if the accumulation register is kept the same through the entire chain. This patch utilizes the A57 FP load balancing pass to enforce that we emit such AES instruction sequence.

http://reviews.llvm.org/D6154

Files:
  lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
  test/CodeGen/AArch64/aes-load-balancing.ll
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