[PATCH] [ARM] [CodeGen] Do not emit intermediate register for zero FP immediate

[Renato Golin]

Hi Sergey,

The inline comments only go live when you click on "Submit" at the bottom of the page. This is to help you make many inline comments and only submit once. So, yeah, I only saw it now. :)

cheers,
--renato

================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:3246
@@ +3245,3 @@
+    // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
+    // created by LowerConstantFP().
+    SDValue BitcastOp = Op->getOperand(0);
----------------
sdmitrouk wrote:
> rengolin wrote:
> > I'd say this is a bit too specific on what LowerConstantFP does today, which may change. Wouldn't any fp bitcast work in this case, if the value being casted is zero?
> Sure, it would work, but how to check node containing initial value for zero without going through all intermediate nodes? I was looking for a way to generalize this check, but didn't find it.
I may be wrong, but wouldn't (Op->getValueType(0) == MVT::f32 || Op->getValueType(0) == MVT::f64) get all cases?

I don't expect vector types here, or half-floats...

http://reviews.llvm.org/D5456