[llvm] r219106 - Add subtarget caches to aarch64, arm, ppc, and x86.
David Blaikie
dblaikie at gmail.com
Mon Oct 6 09:38:29 PDT 2014
On Sun, Oct 5, 2014 at 11:45 PM, Eric Christopher <echristo at gmail.com>
wrote:
> Author: echristo
> Date: Mon Oct 6 01:45:36 2014
> New Revision: 219106
>
> URL: http://llvm.org/viewvc/llvm-project?rev=219106&view=rev
> Log:
> Add subtarget caches to aarch64, arm, ppc, and x86.
> These will make it easier to test further changes to the
> code generation and optimization pipelines as those are
> moved to subtargets initialized with target feature and
> target cpu.
>
<childish whine>Are we /there/ yet?</childish whine>
Does this change the observable behavior of these targets? They would now
start respecting per-function attributes fo feature and cpu? Or is there
some other piece of plumbing needed per target to make these changes live
as you've already done with the MIPS target?
>
> Modified:
> llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
> llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
> llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
> llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> llvm/trunk/lib/Target/X86/X86TargetMachine.h
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Mon Oct 6
> 01:45:36 2014
> @@ -14,6 +14,7 @@
> #include "AArch64TargetMachine.h"
> #include "llvm/CodeGen/Passes.h"
> #include "llvm/CodeGen/RegAllocRegistry.h"
> +#include "llvm/IR/Function.h"
> #include "llvm/PassManager.h"
> #include "llvm/Support/CommandLine.h"
> #include "llvm/Support/TargetRegistry.h"
> @@ -95,7 +96,7 @@ AArch64TargetMachine::AArch64TargetMachi
> CodeGenOpt::Level OL,
> bool LittleEndian)
> : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
> - Subtarget(TT, CPU, FS, *this, LittleEndian),
> + Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian),
> usingPBQP(false) {
> initAsmInfo();
>
> @@ -105,6 +106,32 @@ AArch64TargetMachine::AArch64TargetMachi
> }
> }
>
> +const AArch64Subtarget *
> +AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
> + AttributeSet FnAttrs = F.getAttributes();
> + Attribute CPUAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
> + Attribute FSAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex,
> "target-features");
> +
> + std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
> + ? CPUAttr.getValueAsString().str()
> + : TargetCPU;
> + std::string FS = !FSAttr.hasAttribute(Attribute::None)
> + ? FSAttr.getValueAsString().str()
> + : TargetFS;
> +
> + auto &I = SubtargetMap[CPU + FS];
> + if (!I) {
> + // This needs to be done before we create a new subtarget since any
> + // creation will depend on the TM and the code generation flags on the
> + // function that reside in TargetOptions.
> + resetTargetOptions(F);
> + I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
> isLittle);
> + }
> + return I.get();
> +}
> +
> void AArch64leTargetMachine::anchor() { }
>
> AArch64leTargetMachine::
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h Mon Oct 6
> 01:45:36 2014
> @@ -24,6 +24,7 @@ namespace llvm {
> class AArch64TargetMachine : public LLVMTargetMachine {
> protected:
> AArch64Subtarget Subtarget;
> + mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
>
> public:
> AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
> @@ -34,6 +35,7 @@ public:
> const AArch64Subtarget *getSubtargetImpl() const override {
> return &Subtarget;
> }
> + const AArch64Subtarget *getSubtargetImpl(const Function &F) const
> override;
>
> // Pass Pipeline Configuration
> TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
> @@ -45,6 +47,7 @@ public:
> bool isPBQPUsed() const { return usingPBQP; }
>
> private:
> + bool isLittle;
> bool usingPBQP;
> };
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon Oct 6 01:45:36 2014
> @@ -14,6 +14,7 @@
> #include "ARMTargetMachine.h"
> #include "ARMFrameLowering.h"
> #include "llvm/CodeGen/Passes.h"
> +#include "llvm/IR/Function.h"
> #include "llvm/MC/MCAsmInfo.h"
> #include "llvm/PassManager.h"
> #include "llvm/Support/CommandLine.h"
> @@ -42,7 +43,6 @@ extern "C" void LLVMInitializeARMTarget(
> RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
> }
>
> -
> /// TargetMachine ctor - Create an ARM architecture model.
> ///
> ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
> @@ -51,7 +51,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachi
> Reloc::Model RM,
> CodeModel::Model CM,
> CodeGenOpt::Level OL, bool
> isLittle)
> : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
> - Subtarget(TT, CPU, FS, *this, isLittle) {
> + Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
>
> // Default to triple-appropriate float ABI
> if (Options.FloatABIType == FloatABI::Default)
> @@ -59,6 +59,44 @@ ARMBaseTargetMachine::ARMBaseTargetMachi
> Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
> }
>
> +const ARMSubtarget *
> +ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
> + AttributeSet FnAttrs = F.getAttributes();
> + Attribute CPUAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
> + Attribute FSAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex,
> "target-features");
> +
> + std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
> + ? CPUAttr.getValueAsString().str()
> + : TargetCPU;
> + std::string FS = !FSAttr.hasAttribute(Attribute::None)
> + ? FSAttr.getValueAsString().str()
> + : TargetFS;
> +
> + // FIXME: This is related to the code below to reset the target options,
> + // we need to know whether or not the soft float flag is set on the
> + // function before we can generate a subtarget. We also need to use
> + // it as a key for the subtarget since that can be the only difference
> + // between two functions.
> + Attribute SFAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");
> + bool SoftFloat = !SFAttr.hasAttribute(Attribute::None)
> + ? SFAttr.getValueAsString() == "true"
> + : Options.UseSoftFloat;
> +
> + auto &I = SubtargetMap[CPU + FS + (SoftFloat ? "use-soft-float=true"
> + : "use-soft-float=false")];
> + if (!I) {
> + // This needs to be done before we create a new subtarget since any
> + // creation will depend on the TM and the code generation flags on the
> + // function that reside in TargetOptions.
> + resetTargetOptions(F);
> + I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this,
> isLittle);
> + }
> + return I.get();
> +}
> +
> void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
> // Add first the target-independent BasicTTI pass, then our ARM pass.
> This
> // allows the ARM pass to delegate to the target independent layer when
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Mon Oct 6 01:45:36 2014
> @@ -24,6 +24,9 @@ namespace llvm {
> class ARMBaseTargetMachine : public LLVMTargetMachine {
> protected:
> ARMSubtarget Subtarget;
> + bool isLittle;
> + mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
> +
> public:
> ARMBaseTargetMachine(const Target &T, StringRef TT,
> StringRef CPU, StringRef FS,
> @@ -33,6 +36,7 @@ public:
> bool isLittle);
>
> const ARMSubtarget *getSubtargetImpl() const override { return
> &Subtarget; }
> + const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
>
> /// \brief Register ARM analysis passes with a pass manager.
> void addAnalysisPasses(PassManagerBase &PM) override;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Oct 6 01:45:36
> 2014
> @@ -14,6 +14,7 @@
> #include "PPCTargetMachine.h"
> #include "PPC.h"
> #include "llvm/CodeGen/Passes.h"
> +#include "llvm/IR/Function.h"
> #include "llvm/MC/MCStreamer.h"
> #include "llvm/PassManager.h"
> #include "llvm/Support/CommandLine.h"
> @@ -93,6 +94,31 @@ PPC64TargetMachine::PPC64TargetMachine(c
> : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
> }
>
> +const PPCSubtarget *
> +PPCTargetMachine::getSubtargetImpl(const Function &F) const {
> + AttributeSet FnAttrs = F.getAttributes();
> + Attribute CPUAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
> + Attribute FSAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex,
> "target-features");
> +
> + std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
> + ? CPUAttr.getValueAsString().str()
> + : TargetCPU;
> + std::string FS = !FSAttr.hasAttribute(Attribute::None)
> + ? FSAttr.getValueAsString().str()
> + : TargetFS;
> +
> + auto &I = SubtargetMap[CPU + FS];
> + if (!I) {
> + // This needs to be done before we create a new subtarget since any
> + // creation will depend on the TM and the code generation flags on the
> + // function that reside in TargetOptions.
> + resetTargetOptions(F);
> + I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
> + }
> + return I.get();
> +}
>
>
> //===----------------------------------------------------------------------===//
> // Pass Pipeline Configuration
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Mon Oct 6 01:45:36
> 2014
> @@ -24,7 +24,9 @@ namespace llvm {
> /// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC
> targets.
> ///
> class PPCTargetMachine : public LLVMTargetMachine {
> - PPCSubtarget Subtarget;
> + PPCSubtarget Subtarget;
> +
> + mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
>
> public:
> PPCTargetMachine(const Target &T, StringRef TT,
> @@ -33,6 +35,7 @@ public:
> CodeGenOpt::Level OL);
>
> const PPCSubtarget *getSubtargetImpl() const override { return
> &Subtarget; }
> + const PPCSubtarget *getSubtargetImpl(const Function &F) const override;
>
> // Pass Pipeline Configuration
> TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Oct 6 01:45:36 2014
> @@ -14,6 +14,7 @@
> #include "X86TargetMachine.h"
> #include "X86.h"
> #include "llvm/CodeGen/Passes.h"
> +#include "llvm/IR/Function.h"
> #include "llvm/PassManager.h"
> #include "llvm/Support/CommandLine.h"
> #include "llvm/Support/FormattedStream.h"
> @@ -51,6 +52,45 @@ X86TargetMachine::X86TargetMachine(const
> initAsmInfo();
> }
>
> +const X86Subtarget *
> +X86TargetMachine::getSubtargetImpl(const Function &F) const {
> + AttributeSet FnAttrs = F.getAttributes();
> + Attribute CPUAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
> + Attribute FSAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex,
> "target-features");
> +
> + std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
> + ? CPUAttr.getValueAsString().str()
> + : TargetCPU;
> + std::string FS = !FSAttr.hasAttribute(Attribute::None)
> + ? FSAttr.getValueAsString().str()
> + : TargetFS;
> +
> + // FIXME: This is related to the code below to reset the target options,
> + // we need to know whether or not the soft float flag is set on the
> + // function before we can generate a subtarget. We also need to use
> + // it as a key for the subtarget since that can be the only difference
> + // between two functions.
> + Attribute SFAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");
> + bool SoftFloat = !SFAttr.hasAttribute(Attribute::None)
> + ? SFAttr.getValueAsString() == "true"
> + : Options.UseSoftFloat;
> +
> + auto &I = SubtargetMap[CPU + FS + (SoftFloat ? "use-soft-float=true"
> + : "use-soft-float=false")];
> + if (!I) {
> + // This needs to be done before we create a new subtarget since any
> + // creation will depend on the TM and the code generation flags on the
> + // function that reside in TargetOptions.
> + resetTargetOptions(F);
> + I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
> + Options.StackAlignmentOverride);
> + }
> + return I.get();
> +}
> +
>
> //===----------------------------------------------------------------------===//
> // Command line options for x86
>
> //===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Mon Oct 6 01:45:36 2014
> @@ -26,12 +26,15 @@ class X86TargetMachine final : public LL
> virtual void anchor();
> X86Subtarget Subtarget;
>
> + mutable StringMap<std::unique_ptr<X86Subtarget>> SubtargetMap;
> +
> public:
> X86TargetMachine(const Target &T, StringRef TT,
> StringRef CPU, StringRef FS, const TargetOptions
> &Options,
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL);
> const X86Subtarget *getSubtargetImpl() const override { return
> &Subtarget; }
> + const X86Subtarget *getSubtargetImpl(const Function &F) const override;
>
> /// \brief Register X86 analysis passes with a pass manager.
> void addAnalysisPasses(PassManagerBase &PM) override;
>
>
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