<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Oct 5, 2014 at 11:45 PM, Eric Christopher <span dir="ltr"><<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: echristo<br>
Date: Mon Oct 6 01:45:36 2014<br>
New Revision: 219106<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=219106&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=219106&view=rev</a><br>
Log:<br>
Add subtarget caches to aarch64, arm, ppc, and x86.<br>
These will make it easier to test further changes to the<br>
code generation and optimization pipelines as those are<br>
moved to subtargets initialized with target feature and<br>
target cpu.<br></blockquote><div><br></div><div><childish whine>Are we /there/ yet?</childish whine><br><br>Does this change the observable behavior of these targets? They would now start respecting per-function attributes fo feature and cpu? Or is there some other piece of plumbing needed per target to make these changes live as you've already done with the MIPS target?</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h<br>
llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp<br>
llvm/trunk/lib/Target/ARM/ARMTargetMachine.h<br>
llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h<br>
llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br>
llvm/trunk/lib/Target/X86/X86TargetMachine.h<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Mon Oct 6 01:45:36 2014<br>
@@ -14,6 +14,7 @@<br>
#include "AArch64TargetMachine.h"<br>
#include "llvm/CodeGen/Passes.h"<br>
#include "llvm/CodeGen/RegAllocRegistry.h"<br>
+#include "llvm/IR/Function.h"<br>
#include "llvm/PassManager.h"<br>
#include "llvm/Support/CommandLine.h"<br>
#include "llvm/Support/TargetRegistry.h"<br>
@@ -95,7 +96,7 @@ AArch64TargetMachine::AArch64TargetMachi<br>
CodeGenOpt::Level OL,<br>
bool LittleEndian)<br>
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),<br>
- Subtarget(TT, CPU, FS, *this, LittleEndian),<br>
+ Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian),<br>
usingPBQP(false) {<br>
initAsmInfo();<br>
<br>
@@ -105,6 +106,32 @@ AArch64TargetMachine::AArch64TargetMachi<br>
}<br>
}<br>
<br>
+const AArch64Subtarget *<br>
+AArch64TargetMachine::getSubtargetImpl(const Function &F) const {<br>
+ AttributeSet FnAttrs = F.getAttributes();<br>
+ Attribute CPUAttr =<br>
+ FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");<br>
+ Attribute FSAttr =<br>
+ FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");<br>
+<br>
+ std::string CPU = !CPUAttr.hasAttribute(Attribute::None)<br>
+ ? CPUAttr.getValueAsString().str()<br>
+ : TargetCPU;<br>
+ std::string FS = !FSAttr.hasAttribute(Attribute::None)<br>
+ ? FSAttr.getValueAsString().str()<br>
+ : TargetFS;<br>
+<br>
+ auto &I = SubtargetMap[CPU + FS];<br>
+ if (!I) {<br>
+ // This needs to be done before we create a new subtarget since any<br>
+ // creation will depend on the TM and the code generation flags on the<br>
+ // function that reside in TargetOptions.<br>
+ resetTargetOptions(F);<br>
+ I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);<br>
+ }<br>
+ return I.get();<br>
+}<br>
+<br>
void AArch64leTargetMachine::anchor() { }<br>
<br>
AArch64leTargetMachine::<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h Mon Oct 6 01:45:36 2014<br>
@@ -24,6 +24,7 @@ namespace llvm {<br>
class AArch64TargetMachine : public LLVMTargetMachine {<br>
protected:<br>
AArch64Subtarget Subtarget;<br>
+ mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;<br>
<br>
public:<br>
AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,<br>
@@ -34,6 +35,7 @@ public:<br>
const AArch64Subtarget *getSubtargetImpl() const override {<br>
return &Subtarget;<br>
}<br>
+ const AArch64Subtarget *getSubtargetImpl(const Function &F) const override;<br>
<br>
// Pass Pipeline Configuration<br>
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;<br>
@@ -45,6 +47,7 @@ public:<br>
bool isPBQPUsed() const { return usingPBQP; }<br>
<br>
private:<br>
+ bool isLittle;<br>
bool usingPBQP;<br>
};<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon Oct 6 01:45:36 2014<br>
@@ -14,6 +14,7 @@<br>
#include "ARMTargetMachine.h"<br>
#include "ARMFrameLowering.h"<br>
#include "llvm/CodeGen/Passes.h"<br>
+#include "llvm/IR/Function.h"<br>
#include "llvm/MC/MCAsmInfo.h"<br>
#include "llvm/PassManager.h"<br>
#include "llvm/Support/CommandLine.h"<br>
@@ -42,7 +43,6 @@ extern "C" void LLVMInitializeARMTarget(<br>
RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);<br>
}<br>
<br>
-<br>
/// TargetMachine ctor - Create an ARM architecture model.<br>
///<br>
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,<br>
@@ -51,7 +51,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachi<br>
Reloc::Model RM, CodeModel::Model CM,<br>
CodeGenOpt::Level OL, bool isLittle)<br>
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),<br>
- Subtarget(TT, CPU, FS, *this, isLittle) {<br>
+ Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {<br>
<br>
// Default to triple-appropriate float ABI<br>
if (Options.FloatABIType == FloatABI::Default)<br>
@@ -59,6 +59,44 @@ ARMBaseTargetMachine::ARMBaseTargetMachi<br>
Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;<br>
}<br>
<br>
+const ARMSubtarget *<br>
+ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {<br>
+ AttributeSet FnAttrs = F.getAttributes();<br>
+ Attribute CPUAttr =<br>
+ FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");<br>
+ Attribute FSAttr =<br>
+ FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");<br>
+<br>
+ std::string CPU = !CPUAttr.hasAttribute(Attribute::None)<br>
+ ? CPUAttr.getValueAsString().str()<br>
+ : TargetCPU;<br>
+ std::string FS = !FSAttr.hasAttribute(Attribute::None)<br>
+ ? FSAttr.getValueAsString().str()<br>
+ : TargetFS;<br>
+<br>
+ // FIXME: This is related to the code below to reset the target options,<br>
+ // we need to know whether or not the soft float flag is set on the<br>
+ // function before we can generate a subtarget. We also need to use<br>
+ // it as a key for the subtarget since that can be the only difference<br>
+ // between two functions.<br>
+ Attribute SFAttr =<br>
+ FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");<br>
+ bool SoftFloat = !SFAttr.hasAttribute(Attribute::None)<br>
+ ? SFAttr.getValueAsString() == "true"<br>
+ : Options.UseSoftFloat;<br>
+<br>
+ auto &I = SubtargetMap[CPU + FS + (SoftFloat ? "use-soft-float=true"<br>
+ : "use-soft-float=false")];<br>
+ if (!I) {<br>
+ // This needs to be done before we create a new subtarget since any<br>
+ // creation will depend on the TM and the code generation flags on the<br>
+ // function that reside in TargetOptions.<br>
+ resetTargetOptions(F);<br>
+ I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);<br>
+ }<br>
+ return I.get();<br>
+}<br>
+<br>
void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {<br>
// Add first the target-independent BasicTTI pass, then our ARM pass. This<br>
// allows the ARM pass to delegate to the target independent layer when<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Mon Oct 6 01:45:36 2014<br>
@@ -24,6 +24,9 @@ namespace llvm {<br>
class ARMBaseTargetMachine : public LLVMTargetMachine {<br>
protected:<br>
ARMSubtarget Subtarget;<br>
+ bool isLittle;<br>
+ mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;<br>
+<br>
public:<br>
ARMBaseTargetMachine(const Target &T, StringRef TT,<br>
StringRef CPU, StringRef FS,<br>
@@ -33,6 +36,7 @@ public:<br>
bool isLittle);<br>
<br>
const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }<br>
+ const ARMSubtarget *getSubtargetImpl(const Function &F) const override;<br>
<br>
/// \brief Register ARM analysis passes with a pass manager.<br>
void addAnalysisPasses(PassManagerBase &PM) override;<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Oct 6 01:45:36 2014<br>
@@ -14,6 +14,7 @@<br>
#include "PPCTargetMachine.h"<br>
#include "PPC.h"<br>
#include "llvm/CodeGen/Passes.h"<br>
+#include "llvm/IR/Function.h"<br>
#include "llvm/MC/MCStreamer.h"<br>
#include "llvm/PassManager.h"<br>
#include "llvm/Support/CommandLine.h"<br>
@@ -93,6 +94,31 @@ PPC64TargetMachine::PPC64TargetMachine(c<br>
: PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {<br>
}<br>
<br>
+const PPCSubtarget *<br>
+PPCTargetMachine::getSubtargetImpl(const Function &F) const {<br>
+ AttributeSet FnAttrs = F.getAttributes();<br>
+ Attribute CPUAttr =<br>
+ FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");<br>
+ Attribute FSAttr =<br>
+ FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");<br>
+<br>
+ std::string CPU = !CPUAttr.hasAttribute(Attribute::None)<br>
+ ? CPUAttr.getValueAsString().str()<br>
+ : TargetCPU;<br>
+ std::string FS = !FSAttr.hasAttribute(Attribute::None)<br>
+ ? FSAttr.getValueAsString().str()<br>
+ : TargetFS;<br>
+<br>
+ auto &I = SubtargetMap[CPU + FS];<br>
+ if (!I) {<br>
+ // This needs to be done before we create a new subtarget since any<br>
+ // creation will depend on the TM and the code generation flags on the<br>
+ // function that reside in TargetOptions.<br>
+ resetTargetOptions(F);<br>
+ I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);<br>
+ }<br>
+ return I.get();<br>
+}<br>
<br>
//===----------------------------------------------------------------------===//<br>
// Pass Pipeline Configuration<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Mon Oct 6 01:45:36 2014<br>
@@ -24,7 +24,9 @@ namespace llvm {<br>
/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.<br>
///<br>
class PPCTargetMachine : public LLVMTargetMachine {<br>
- PPCSubtarget Subtarget;<br>
+ PPCSubtarget Subtarget;<br>
+<br>
+ mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;<br>
<br>
public:<br>
PPCTargetMachine(const Target &T, StringRef TT,<br>
@@ -33,6 +35,7 @@ public:<br>
CodeGenOpt::Level OL);<br>
<br>
const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }<br>
+ const PPCSubtarget *getSubtargetImpl(const Function &F) const override;<br>
<br>
// Pass Pipeline Configuration<br>
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=219106&r1=219105&r2=219106&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Oct 6 01:45:36 2014<br>
@@ -14,6 +14,7 @@<br>
#include "X86TargetMachine.h"<br>
#include "X86.h"<br>
#include "llvm/CodeGen/Passes.h"<br>
+#include "llvm/IR/Function.h"<br>
#include "llvm/PassManager.h"<br>
#include "llvm/Support/CommandLine.h"<br>
#include "llvm/Support/FormattedStream.h"<br>
@@ -51,6 +52,45 @@ X86TargetMachine::X86TargetMachine(const<br>
initAsmInfo();<br>
}<br>
<br>
+const X86Subtarget *<br>
+X86TargetMachine::getSubtargetImpl(const Function &F) const {<br>
+ AttributeSet FnAttrs = F.getAttributes();<br>
+ Attribute CPUAttr =<br>
+ FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");<br>
+ Attribute FSAttr =<br>
+ FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");<br>
+<br>
+ std::string CPU = !CPUAttr.hasAttribute(Attribute::None)<br>
+ ? CPUAttr.getValueAsString().str()<br>
+ : TargetCPU;<br>
+ std::string FS = !FSAttr.hasAttribute(Attribute::None)<br>
+ ? FSAttr.getValueAsString().str()<br>
+ : TargetFS;<br>
+<br>
+ // FIXME: This is related to the code below to reset the target options,<br>
+ // we need to know whether or not the soft float flag is set on the<br>
+ // function before we can generate a subtarget. We also need to use<br>
+ // it as a key for the subtarget since that can be the only difference<br>
+ // between two functions.<br>
+ Attribute SFAttr =<br>
+ FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");<br>
+ bool SoftFloat = !SFAttr.hasAttribute(Attribute::None)<br>
+ ? SFAttr.getValueAsString() == "true"<br>
+ : Options.UseSoftFloat;<br>
+<br>
+ auto &I = SubtargetMap[CPU + FS + (SoftFloat ? "use-soft-float=true"<br>
+ : "use-soft-float=false")];<br>
+ if (!I) {<br>
+ // This needs to be done before we create a new subtarget since any<br>
+ // creation will depend on the TM and the code generation flags on the<br>
+ // function that reside in TargetOptions.<br>
+ resetTargetOptions(F);<br>
+ I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,<br>
+ Options.StackAlignmentOverride);<br>
+ }<br>
+ return I.get();<br>
+}<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// Command line options for x86<br>
//===----------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=219106&r1=219105&r2=219106&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Mon Oct 6 01:45:36 2014<br>
@@ -26,12 +26,15 @@ class X86TargetMachine final : public LL<br>
virtual void anchor();<br>
X86Subtarget Subtarget;<br>
<br>
+ mutable StringMap<std::unique_ptr<X86Subtarget>> SubtargetMap;<br>
+<br>
public:<br>
X86TargetMachine(const Target &T, StringRef TT,<br>
StringRef CPU, StringRef FS, const TargetOptions &Options,<br>
Reloc::Model RM, CodeModel::Model CM,<br>
CodeGenOpt::Level OL);<br>
const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }<br>
+ const X86Subtarget *getSubtargetImpl(const Function &F) const override;<br>
<br>
/// \brief Register X86 analysis passes with a pass manager.<br>
void addAnalysisPasses(PassManagerBase &PM) override;<br>
<br>
<br>
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</blockquote></div><br></div></div>