[PATCH] Fix TableGen -gen-disassembler output for certain bit field definitions.

[Tom Stellard]

On Fri, Sep 26, 2014 at 03:07:16AM +0000, Steve King wrote:
> TableGen -gen-disassembler extracts incorrect operand values for certain bit fields with an offset.  The result is that disassembly silently fails with incorrect operand values.  Bit assignments like:
> Inst{7-0} = Foo{9-2}
> are vulnerable to this problem.
> 

Tablegen has !shl and !srl operators, I think it would be good to add test
cases using those too.

-Tom

> http://reviews.llvm.org/D5498
> 
> Files:
>   test/TableGen/BitShiftDecoder.td
>   utils/TableGen/FixedLenDecoderEmitter.cpp

> Index: test/TableGen/BitShiftDecoder.td
> ===================================================================
> --- /dev/null
> +++ test/TableGen/BitShiftDecoder.td
> @@ -0,0 +1,64 @@
> +// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
> +
> +include "llvm/Target/Target.td"
> +
> +def archInstrInfo : InstrInfo { }
> +
> +def arch : Target {
> +    let InstructionSet = archInstrInfo;
> +}
> +
> +def  Myi32  : Operand<i32> {
> +  let DecoderMethod = "DecodeMyi32";
> +}
> +
> +
> +let OutOperandList = (outs), Size = 2 in {
> +
> +def foo : Instruction {
> +    let InOperandList = (ins i32imm:$factor);
> +    field bits<16> Inst;
> +    bits<32> factor;
> +    let Inst{7-0} = 0xAA;
> +    let Inst{14-8} = factor{6-0}; // no shift
> +    let AsmString = "foo  $factor";
> +    field bits<16> SoftFail = 0;
> +    }
> +
> +def bar : Instruction {
> +    let InOperandList = (ins i32imm:$factor);
> +    field bits<16> Inst;
> +    bits<32> factor;
> +    let Inst{7-0} = 0xBB;
> +    let Inst{15-8} = factor{10-3}; // shift by 3
> +    let AsmString = "bar  $factor";
> +    field bits<16> SoftFail = 0;
> +    }
> +
> +def biz : Instruction {
> +    let InOperandList = (ins i32imm:$factor);
> +    field bits<16> Inst;
> +    bits<32> factor;
> +    let Inst{7-0} = 0xCC;
> +    let Inst{11-8,15-12} = factor{10-3}; // shift by 3, multipart
> +    let AsmString = "biz  $factor";
> +    field bits<16> SoftFail = 0;
> +    }
> +
> +def baz : Instruction {
> +    let InOperandList = (ins Myi32:$factor);
> +    field bits<16> Inst;
> +    bits<32> factor;
> +    let Inst{7-0} = 0xDD;
> +    let Inst{15-8} = factor{11-4}; // shift by 4 + custom decode
> +    let AsmString = "baz  $factor";
> +    field bits<16> SoftFail = 0;
> +    }
> +}
> +
> +
> +// CHECK: tmp = fieldFromInstruction(insn, 8, 7);
> +// CHECK: tmp = fieldFromInstruction(insn, 8, 8) << 3;
> +// CHECK: tmp |= (fieldFromInstruction(insn, 8, 4) << 7);
> +// CHECK: tmp |= (fieldFromInstruction(insn, 12, 4) << 3);
> +// CHECK: tmp = fieldFromInstruction(insn, 8, 8) << 4;
> \ No newline at end of file
> Index: utils/TableGen/FixedLenDecoderEmitter.cpp
> ===================================================================
> --- utils/TableGen/FixedLenDecoderEmitter.cpp
> +++ utils/TableGen/FixedLenDecoderEmitter.cpp
> @@ -1051,7 +1051,11 @@
>      OperandInfo::const_iterator OI = OpInfo.begin();
>      o.indent(Indentation) << "tmp = fieldFromInstruction"
>                            << "(insn, " << OI->Base << ", " << OI->Width
> -                          << ");\n";
> +                          << ")";
> +    if (OI->Offset)
> +      o << " << " << OI->Offset;
> +    o << ";\n";
> +
>    } else {
>      o.indent(Indentation) << "tmp = 0;\n";
>      for (OperandInfo::const_iterator OI = OpInfo.begin(), OE = OpInfo.end();

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