[llvm] r217249 - R600/SI: Fix bug in SIInstrInfo::legalizeOpWithMove()

[Tom Stellard]

Author: tstellar
Date: Fri Sep  5 09:08:01 2014
New Revision: 217249

URL: http://llvm.org/viewvc/llvm-project?rev=217249&view=rev
Log:
R600/SI: Fix bug in SIInstrInfo::legalizeOpWithMove()

We must constrain the destination register class of legalized operands
to a VGPR class or else the illegal operand may be folded back into
the instruction by the register coalescer.

This fixes a bug in add.ll that will be uncovered by future commits.

Modified:
    llvm/trunk/lib/Target/R600/SIInstrInfo.cpp

Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.cpp?rev=217249&r1=217248&r2=217249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.cpp Fri Sep  5 09:08:01 2014
@@ -984,17 +984,18 @@ void SIInstrInfo::legalizeOpWithMove(Mac
   unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
   const TargetRegisterClass *RC = RI.getRegClass(RCID);
   unsigned Opcode = AMDGPU::V_MOV_B32_e32;
-
   if (MO.isReg()) {
     Opcode = AMDGPU::COPY;
   } else if (RI.isSGPRClass(RC)) {
     Opcode = AMDGPU::S_MOV_B32;
-  } else if (MO.isImm()) {
-    if (RC == &AMDGPU::VSrc_32RegClass)
-      Opcode = AMDGPU::S_MOV_B32;
   }
 
   const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
+  if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) {
+    VRC = &AMDGPU::VReg_64RegClass;
+  } else {
+    VRC = &AMDGPU::VReg_32RegClass;
+  }
   unsigned Reg = MRI.createVirtualRegister(VRC);
   BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
           Reg).addOperand(MO);