[PATCH][X86][Haswell][SchedModel] Add exceptions for instructions that diverge from the generic model.

[Quentin Colombet]

Thanks Nadav!

This is r215904 to r215924.

-Quentin
> On Aug 18, 2014, at 10:07 AM, Nadav Rotem <nrotem at apple.com> wrote:
> 
> Thank you for looking at this Quentin. The patch LGTM. 
> 
>> On Aug 18, 2014, at 10:06 AM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote:
>> 
>> Ping?
>> 
>> Thanks,
>> -Quentin
>> 
>> On Aug 12, 2014, at 10:04 AM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote:
>> 
>>> Hi Nadav,
>>> 
>>> On Aug 12, 2014, at 9:29 AM, Nadav Rotem <nrotem at apple.com <mailto:nrotem at apple.com>> wrote:
>>> 
>>>> Hi Quentin, 
>>>> 
>>>> Sorry for the delay in response. Thanks for taking the time to work on improving the scheduling model for x86. 
>>> 
>>> Thanks for taking a look!
>>> 
>>>> 
>>>>> On Aug 8, 2014, at 5:10 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote:
>>>>> 
>>>>> Hi,
>>>>> 
>>>>> This series of patches adds an exception for each instruction that diverges from the generic scheduling model.
>>>>> It follows the structure of Agner Fog’s instructions tables and provides a patch for each sub-group.
>>>> 
>>>> Did you use Agner’s tables or the tables from the intel optimization guide? 
>>> 
>>> I used Agner’s tables. As far as I can tell the intel optimization guide is not precise enough for this level of details. Moreover, Agner’s data are based on actual measurements :).
>>> 
>>> Cheers,
>>> -Quentin
>>>> 
>>>>> 
>>>>> Although I had observed changes of the schedule of some test cases in the llvm-testsuite + SPECs, I had not measured anything than noise.
>>>>> Note: I have measured both ‘-O3 -march=native' and ‘-Os -march=native’ on a Haswell machine.
>>>> 
>>>> :( 
>>>> 
>>>>> 
>>>>> Thanks for your reviews.
>>>>> 
>>>>> -Quentin
>>>>> <0001-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0002-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0003-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0004-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0005-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0006-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0007-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0008-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0009-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0010-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0011-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0012-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0013-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0014-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0015-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0016-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0017-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0018-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0019-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0020-X86-Haswell-SchedModel-Add-architecture-specific-sch.patch><0021-X86-Haswell-SchedModel-Tidy-up.patch>
>>>> 
>>> 
>>> 
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