[AArch64] FP load balancing pass for Cortex-A57

[James Molloy]

Apparently I have an itchy trigger-finger today.

 

Now with attached patch!

 

From: James Molloy 
Sent: 05 August 2014 13:51
To: Tim Northover
Cc: llvm-commits
Subject: [AArch64] FP load balancing pass for Cortex-A57

 

Hi Tim,

 

For best-case performance on Cortex-A57, we should try to use a balanced mix
of odd and even D-registers when performing a critical sequence of
independent, non-quadword FP/ASIMD floating-point multiply or
multiply-accumulate operations.

 

This pass attempts to detect situations where the register allocation may
adversely affect this load balancing and to change the registers used so as
to better utilize the CPU.

 

Ideally we'd just take each multiply or multiply-accumulate in turn and
allocate it alternating even or odd registers. However, multiply-accumulates
are most efficiently performed in the same functional unit as their
accumulation operand. Therefore this pass tries to find maximal sequences
("Chains") of multiply-accumulates linked via their accumulation operand,
and assign them all the same "color" (oddness/evenness).

 

This optimization affects S-register and D-register floating point
multiplies and FMADD/FMAs, as well as vector (floating point only) muls and
FMADD/FMA. Q register instructions (and 128-bit vector instructions) are not
affected.

 

This patch has been reviewed off-list by Silviu Baranga and Jiangning Liu,
and I have their LGTM.

 

Do you have any thoughts yourself?

 

Cheers,

 

James
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