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</o:shapelayout></xml><![endif]--></head><body lang=EN-GB link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='color:#1F497D'>Apparently I have an itchy trigger-finger today.<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='color:#1F497D'>Now with attached patch!<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif";mso-fareast-language:EN-GB'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif";mso-fareast-language:EN-GB'> James Molloy <br><b>Sent:</b> 05 August 2014 13:51<br><b>To:</b> Tim Northover<br><b>Cc:</b> llvm-commits<br><b>Subject:</b> [AArch64] FP load balancing pass for Cortex-A57<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Hi Tim,<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>For best-case performance on Cortex-A57, we should try to use a balanced mix of odd and even D-registers when performing a critical sequence of independent, non-quadword FP/ASIMD floating-point multiply or multiply-accumulate operations.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>This pass attempts to detect situations where the register allocation may adversely affect this load balancing and to change the registers used so as to better utilize the CPU.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Ideally we'd just take each multiply or multiply-accumulate in turn and allocate it alternating even or odd registers. However, multiply-accumulates are most efficiently performed in the same functional unit as their accumulation operand. Therefore this pass tries to find maximal sequences ("Chains") of multiply-accumulates linked via their accumulation operand, and assign them all the same "color" (oddness/evenness).<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>This optimization affects S-register and D-register floating point multiplies and FMADD/FMAs, as well as vector (floating point only) muls and FMADD/FMA. Q register instructions (and 128-bit vector instructions) are not affected.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>This patch has been reviewed off-list by Silviu Baranga and Jiangning Liu, and I have their LGTM.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Do you have any thoughts yourself?<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Cheers,<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>James<o:p></o:p></p></div></body></html>