[PATCH] [AArch64] Add instruction selection support for ADDV (add across vector).

[Evan Cheng]

I would expect / prefer to see this being handled with SLP vectorization. That is, SLP vectorizer should match this to horizontal reduction fadd and than isel can map it to the right instruction. That way, we have a more general solution for all targets.

I see x86 isel has code to handle horizontal float add / sub.

Evan

On Jun 17, 2014, at 9:24 AM, Tilmann Scheller <t.scheller at samsung.com> wrote:

> Hi,
> 
> attached is a patch for PR20035 (instruction selection support for horizontal adds).
> 
> Regards,
> 
> Tilmann
> 
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