[llvm] r211182 - R600: Custom lower f64 frint for pre-CI
Kaelyn Takata
rikka at google.com
Wed Jun 18 11:01:23 PDT 2014
Matt,
This commit appears to break builds with -Werror enabled (at least when
building with clang):
~/llvm/lib/Target/R600/AMDGPUISelLowering.cpp:1667:34: error: hexadecimal
floating
constants are a C99 feature [-Werror,-Wc99-extensions]
SDValue C1 = DAG.getConstantFP(0x1.0p+52, MVT::f64);
^
~/llvm/lib/Target/R600/AMDGPUISelLowering.cpp:1674:34: error: hexadecimal
floating
constants are a C99 feature [-Werror,-Wc99-extensions]
SDValue C2 = DAG.getConstantFP(0x1.fffffffffffffp+51, MVT::f64);
On Wed, Jun 18, 2014 at 10:05 AM, Matt Arsenault <Matthew.Arsenault at amd.com>
wrote:
> Author: arsenm
> Date: Wed Jun 18 12:05:26 2014
> New Revision: 211182
>
> URL: http://llvm.org/viewvc/llvm-project?rev=211182&view=rev
> Log:
> R600: Custom lower f64 frint for pre-CI
>
> Modified:
> llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
> llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h
> llvm/trunk/test/CodeGen/R600/llvm.rint.f64.ll
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=211182&r1=211181&r2=211182&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Wed Jun 18 12:05:26
> 2014
> @@ -218,6 +218,10 @@ AMDGPUTargetLowering::AMDGPUTargetLoweri
>
> setOperationAction(ISD::BR_CC, MVT::i1, Expand);
>
> + if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
> + setOperationAction(ISD::FRINT, MVT::f64, Custom);
> + }
> +
> if (!Subtarget->hasBFI()) {
> // fcopysign can be done in a single instruction with BFI.
> setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
> @@ -490,6 +494,7 @@ SDValue AMDGPUTargetLowering::LowerOpera
> case ISD::SDIV: return LowerSDIV(Op, DAG);
> case ISD::SREM: return LowerSREM(Op, DAG);
> case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
> + case ISD::FRINT: return LowerFRINT(Op, DAG);
> case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
>
> // AMDIL DAG lowering.
> @@ -1566,6 +1571,27 @@ SDValue AMDGPUTargetLowering::LowerUDIVR
> return DAG.getMergeValues(Ops, DL);
> }
>
> +SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG)
> const {
> + SDLoc SL(Op);
> + SDValue Src = Op.getOperand(0);
> +
> + assert(Op.getValueType() == MVT::f64);
> +
> + SDValue C1 = DAG.getConstantFP(0x1.0p+52, MVT::f64);
> + SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
> +
> + SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
> + SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
> +
> + SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
> + SDValue C2 = DAG.getConstantFP(0x1.fffffffffffffp+51, MVT::f64);
> +
> + EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
> + SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
> +
> + return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
> +}
> +
> SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
> SelectionDAG &DAG) const {
> SDValue S0 = Op.getOperand(0);
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h?rev=211182&r1=211181&r2=211182&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h Wed Jun 18 12:05:26
> 2014
> @@ -51,6 +51,7 @@ private:
> SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
> SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
> SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
> + SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
> SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
>
> SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
>
> Modified: llvm/trunk/test/CodeGen/R600/llvm.rint.f64.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.rint.f64.ll?rev=211182&r1=211181&r2=211182&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/llvm.rint.f64.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/llvm.rint.f64.ll Wed Jun 18 12:05:26 2014
> @@ -1,30 +1,38 @@
> ; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs < %s |
> FileCheck -check-prefix=CI -check-prefix=FUNC %s
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck
> -check-prefix=SI -check-prefix=FUNC %s
>
> -; FUNC-LABEL: @f64
> +; FUNC-LABEL: @rint_f64
> ; CI: V_RNDNE_F64_e32
> -define void @f64(double addrspace(1)* %out, double %in) {
> +
> +; SI-DAG: V_ADD_F64
> +; SI-DAG: V_ADD_F64
> +; SI-DAG V_CMP_GT_F64_e64
> +; SI: V_CNDMASK_B32
> +; SI: V_CNDMASK_B32
> +; SI: S_ENDPGM
> +define void @rint_f64(double addrspace(1)* %out, double %in) {
> entry:
> %0 = call double @llvm.rint.f64(double %in)
> store double %0, double addrspace(1)* %out
> ret void
> }
>
> -; FUNC-LABEL: @v2f64
> +; FUNC-LABEL: @rint_v2f64
> ; CI: V_RNDNE_F64_e32
> ; CI: V_RNDNE_F64_e32
> -define void @v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
> +define void @rint_v2f64(<2 x double> addrspace(1)* %out, <2 x double>
> %in) {
> entry:
> %0 = call <2 x double> @llvm.rint.v2f64(<2 x double> %in)
> store <2 x double> %0, <2 x double> addrspace(1)* %out
> ret void
> }
>
> -; FUNC-LABEL: @v4f64
> +; FUNC-LABEL: @rint_v4f64
> ; CI: V_RNDNE_F64_e32
> ; CI: V_RNDNE_F64_e32
> ; CI: V_RNDNE_F64_e32
> ; CI: V_RNDNE_F64_e32
> -define void @v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
> +define void @rint_v4f64(<4 x double> addrspace(1)* %out, <4 x double>
> %in) {
> entry:
> %0 = call <4 x double> @llvm.rint.v4f64(<4 x double> %in)
> store <4 x double> %0, <4 x double> addrspace(1)* %out
>
>
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