<div dir="ltr">Matt,<div><br></div><div>This commit appears to break builds with -Werror enabled (at least when building with clang):<div><br></div><div><div>~/llvm/lib/Target/R600/AMDGPUISelLowering.cpp:1667:34: error: hexadecimal floating</div>
<div>
constants are a C99 feature [-Werror,-Wc99-extensions]</div><div> SDValue C1 = DAG.getConstantFP(0x1.0p+52, MVT::f64);</div><div> ^</div><div>~/llvm/lib/Target/R600/AMDGPUISelLowering.cpp:1674:34: error: hexadecimal floating</div>
<div> constants are a C99 feature [-Werror,-Wc99-extensions]</div><div> SDValue C2 = DAG.getConstantFP(0x1.fffffffffffffp+51, MVT::f64);</div></div><div><br></div></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">
On Wed, Jun 18, 2014 at 10:05 AM, Matt Arsenault <span dir="ltr"><<a href="mailto:Matthew.Arsenault@amd.com" target="_blank">Matthew.Arsenault@amd.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: arsenm<br>
Date: Wed Jun 18 12:05:26 2014<br>
New Revision: 211182<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=211182&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=211182&view=rev</a><br>
Log:<br>
R600: Custom lower f64 frint for pre-CI<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp<br>
llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h<br>
llvm/trunk/test/CodeGen/R600/llvm.rint.f64.ll<br>
<br>
Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=211182&r1=211181&r2=211182&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=211182&r1=211181&r2=211182&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Wed Jun 18 12:05:26 2014<br>
@@ -218,6 +218,10 @@ AMDGPUTargetLowering::AMDGPUTargetLoweri<br>
<br>
setOperationAction(ISD::BR_CC, MVT::i1, Expand);<br>
<br>
+ if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {<br>
+ setOperationAction(ISD::FRINT, MVT::f64, Custom);<br>
+ }<br>
+<br>
if (!Subtarget->hasBFI()) {<br>
// fcopysign can be done in a single instruction with BFI.<br>
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);<br>
@@ -490,6 +494,7 @@ SDValue AMDGPUTargetLowering::LowerOpera<br>
case ISD::SDIV: return LowerSDIV(Op, DAG);<br>
case ISD::SREM: return LowerSREM(Op, DAG);<br>
case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);<br>
+ case ISD::FRINT: return LowerFRINT(Op, DAG);<br>
case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);<br>
<br>
// AMDIL DAG lowering.<br>
@@ -1566,6 +1571,27 @@ SDValue AMDGPUTargetLowering::LowerUDIVR<br>
return DAG.getMergeValues(Ops, DL);<br>
}<br>
<br>
+SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {<br>
+ SDLoc SL(Op);<br>
+ SDValue Src = Op.getOperand(0);<br>
+<br>
+ assert(Op.getValueType() == MVT::f64);<br>
+<br>
+ SDValue C1 = DAG.getConstantFP(0x1.0p+52, MVT::f64);<br>
+ SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);<br>
+<br>
+ SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);<br>
+ SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);<br>
+<br>
+ SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);<br>
+ SDValue C2 = DAG.getConstantFP(0x1.fffffffffffffp+51, MVT::f64);<br>
+<br>
+ EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);<br>
+ SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);<br>
+<br>
+ return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);<br>
+}<br>
+<br>
SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,<br>
SelectionDAG &DAG) const {<br>
SDValue S0 = Op.getOperand(0);<br>
<br>
Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h?rev=211182&r1=211181&r2=211182&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h?rev=211182&r1=211181&r2=211182&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h Wed Jun 18 12:05:26 2014<br>
@@ -51,6 +51,7 @@ private:<br>
SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;<br>
SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;<br>
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;<br>
+ SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;<br>
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;<br>
<br>
SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,<br>
<br>
Modified: llvm/trunk/test/CodeGen/R600/llvm.rint.f64.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.rint.f64.ll?rev=211182&r1=211181&r2=211182&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.rint.f64.ll?rev=211182&r1=211181&r2=211182&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/R600/llvm.rint.f64.ll (original)<br>
+++ llvm/trunk/test/CodeGen/R600/llvm.rint.f64.ll Wed Jun 18 12:05:26 2014<br>
@@ -1,30 +1,38 @@<br>
; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s<br>
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s<br>
<br>
-; FUNC-LABEL: @f64<br>
+; FUNC-LABEL: @rint_f64<br>
; CI: V_RNDNE_F64_e32<br>
-define void @f64(double addrspace(1)* %out, double %in) {<br>
+<br>
+; SI-DAG: V_ADD_F64<br>
+; SI-DAG: V_ADD_F64<br>
+; SI-DAG V_CMP_GT_F64_e64<br>
+; SI: V_CNDMASK_B32<br>
+; SI: V_CNDMASK_B32<br>
+; SI: S_ENDPGM<br>
+define void @rint_f64(double addrspace(1)* %out, double %in) {<br>
entry:<br>
%0 = call double @llvm.rint.f64(double %in)<br>
store double %0, double addrspace(1)* %out<br>
ret void<br>
}<br>
<br>
-; FUNC-LABEL: @v2f64<br>
+; FUNC-LABEL: @rint_v2f64<br>
; CI: V_RNDNE_F64_e32<br>
; CI: V_RNDNE_F64_e32<br>
-define void @v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {<br>
+define void @rint_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {<br>
entry:<br>
%0 = call <2 x double> @llvm.rint.v2f64(<2 x double> %in)<br>
store <2 x double> %0, <2 x double> addrspace(1)* %out<br>
ret void<br>
}<br>
<br>
-; FUNC-LABEL: @v4f64<br>
+; FUNC-LABEL: @rint_v4f64<br>
; CI: V_RNDNE_F64_e32<br>
; CI: V_RNDNE_F64_e32<br>
; CI: V_RNDNE_F64_e32<br>
; CI: V_RNDNE_F64_e32<br>
-define void @v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {<br>
+define void @rint_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {<br>
entry:<br>
%0 = call <4 x double> @llvm.rint.v4f64(<4 x double> %in)<br>
store <4 x double> %0, <4 x double> addrspace(1)* %out<br>
<br>
<br>
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</blockquote></div><br></div>