[PATCH] ARMEB: Vector extend operations

[James Molloy]

Hi Christian,

I don't think this patch is correct.

+  def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
+                    (!cast<PatFrag>("extloadvi" # SrcTy) addrmode6:$addr)),
+                  (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
+                    (!cast<Instruction>("VREV64d" # SrcTy)
+                      (!cast<Instruction>("VLD1d" # SrcTy)
addrmode6:$addr)))>;

Currently, we'll generate, for an extload:

    vld1.i8 d0, [...]
    vmovl.u16 d0, d0

I think this is correct. We load "as-if" LD1, and the second instruction
does not permute the lanes. With your change, we'll generate:

    vld1.i8 d0, [...]
    vrev.64 d0, d0
    vmovl.u16 d0, d0

Which I think is wrong - it is "as-if" VLDR.

Some of the other cases in your patch, where we're doing a *scalar* load
and converting it to a vector, are valid I think. But this one at least is
not.

Cheers,

James


On 16 June 2014 12:21, Christian Pirker <cpirker at a-bix.com> wrote:

> Updated summary and added some source comments.
>
> http://reviews.llvm.org/D4043
>
> Files:
>   lib/Target/ARM/ARMISelLowering.cpp
>   lib/Target/ARM/ARMInstrNEON.td
>   test/CodeGen/ARM/big-endian-neon-extend.ll
>
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