[llvm] r210998 - R600: Move / cleanup more leftover AMDIL stuff.
Jan Vesely
jan.vesely at rutgers.edu
Sun Jun 15 14:19:19 PDT 2014
On Sun, 2014-06-15 at 20:23 +0000, Matt Arsenault wrote:
> Author: arsenm
> Date: Sun Jun 15 15:23:38 2014
> New Revision: 210998
>
> URL: http://llvm.org/viewvc/llvm-project?rev=210998&view=rev
> Log:
> R600: Move / cleanup more leftover AMDIL stuff.
>
> Modified:
> llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
> llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h
> llvm/trunk/lib/Target/R600/AMDILISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=210998&r1=210997&r2=210998&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Sun Jun 15 15:23:38 2014
> @@ -348,6 +348,19 @@ MVT AMDGPUTargetLowering::getVectorIdxTy
> return MVT::i32;
> }
>
> +// The backend supports 32 and 64 bit floating point immediates.
> +// FIXME: Why are we reporting vectors of FP immediates as legal?
> +bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
> + EVT ScalarVT = VT.getScalarType();
> + return (ScalarVT == MVT::f32 || MVT::f64);
Shouldn't this be (ScalarVT == MVT::f32 || ScalarVT == MVT::f64); ?
> +}
> +
> +// We don't want to shrink f64 / f32 constants.
> +bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
> + EVT ScalarVT = VT.getScalarType();
> + return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
> +}
> +
> bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
> EVT CastTy) const {
> if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
> @@ -455,18 +468,16 @@ SDValue AMDGPUTargetLowering::LowerCall(
> return SDValue();
> }
>
> -SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
> - const {
> +SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
> + SelectionDAG &DAG) const {
> switch (Op.getOpcode()) {
> default:
> Op.getNode()->dump();
> llvm_unreachable("Custom lowering code for this"
> "instruction is not implemented yet!");
> break;
> - // AMDIL DAG lowering
> + // AMDGPU DAG lowering.
> case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
> - case ISD::BRCOND: return LowerBRCOND(Op, DAG);
> - // AMDGPU DAG lowering
> case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
> case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
> case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
> @@ -475,6 +486,9 @@ SDValue AMDGPUTargetLowering::LowerOpera
> case ISD::SREM: return LowerSREM(Op, DAG);
> case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
> case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
> +
> + // AMDIL DAG lowering.
> + case ISD::BRCOND: return LowerBRCOND(Op, DAG);
> }
> return Op;
> }
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h?rev=210998&r1=210997&r2=210998&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h Sun Jun 15 15:23:38 2014
> @@ -53,6 +53,11 @@ private:
> SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
> SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
>
> + SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
> + unsigned BitsDiff,
> + SelectionDAG &DAG) const;
> + SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
> +
> protected:
> static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
> static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
> @@ -101,6 +106,10 @@ public:
> bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
>
> MVT getVectorIdxTy() const override;
> +
> + bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
> + bool ShouldShrinkFPConstant(EVT VT) const override;
> +
> bool isLoadBitCastBeneficial(EVT, EVT) const override;
> SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
> bool isVarArg,
> @@ -111,6 +120,7 @@ public:
> SmallVectorImpl<SDValue> &InVals) const override;
>
> SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
> + SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
> void ReplaceNodeResults(SDNode * N,
> SmallVectorImpl<SDValue> &Results,
> SelectionDAG &DAG) const override;
> @@ -139,26 +149,9 @@ public:
> const SelectionDAG &DAG,
> unsigned Depth = 0) const override;
>
> -// Functions defined in AMDILISelLowering.cpp
> -public:
> - bool getTgtMemIntrinsic(IntrinsicInfo &Info,
> - const CallInst &I, unsigned Intrinsic) const override;
> -
> - /// We want to mark f32/f64 floating point values as legal.
> - bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
> -
> - /// We don't want to shrink f64/f32 constants.
> - bool ShouldShrinkFPConstant(EVT VT) const override;
> -
> - SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
> -
> private:
> + // Functions defined in AMDILISelLowering.cpp
> void InitAMDILLowering();
> -
> - SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
> - unsigned BitsDiff,
> - SelectionDAG &DAG) const;
> - SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
> SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
> };
>
>
> Modified: llvm/trunk/lib/Target/R600/AMDILISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDILISelLowering.cpp?rev=210998&r1=210997&r2=210998&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDILISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/AMDILISelLowering.cpp Sun Jun 15 15:23:38 2014
> @@ -13,27 +13,10 @@
> //===----------------------------------------------------------------------===//
>
> #include "AMDGPUISelLowering.h"
> -#include "AMDGPURegisterInfo.h"
> #include "AMDGPUSubtarget.h"
> -#include "AMDILIntrinsicInfo.h"
> -#include "llvm/CodeGen/MachineFrameInfo.h"
> -#include "llvm/CodeGen/MachineRegisterInfo.h"
> -#include "llvm/CodeGen/PseudoSourceValue.h"
> #include "llvm/CodeGen/SelectionDAG.h"
> -#include "llvm/CodeGen/SelectionDAGNodes.h"
> -#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
> -#include "llvm/IR/CallingConv.h"
> -#include "llvm/IR/DerivedTypes.h"
> -#include "llvm/IR/Instructions.h"
> -#include "llvm/IR/Intrinsics.h"
> -#include "llvm/Support/raw_ostream.h"
> -#include "llvm/Target/TargetInstrInfo.h"
> -#include "llvm/Target/TargetOptions.h"
>
> using namespace llvm;
> -//===----------------------------------------------------------------------===//
> -// TargetLowering Implementation Help Functions End
> -//===----------------------------------------------------------------------===//
>
> //===----------------------------------------------------------------------===//
> // TargetLowering Class Implementation Begins
> @@ -111,37 +94,6 @@ void AMDGPUTargetLowering::InitAMDILLowe
> setSelectIsExpensive(true); // FIXME: This makes no sense at all
> }
>
> -bool
> -AMDGPUTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
> - const CallInst &I, unsigned Intrinsic) const {
> - return false;
> -}
> -
> -// The backend supports 32 and 64 bit floating point immediates
> -bool
> -AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
> - if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32
> - || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) {
> - return true;
> - } else {
> - return false;
> - }
> -}
> -
> -bool
> -AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
> - if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32
> - || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) {
> - return false;
> - } else {
> - return true;
> - }
> -}
> -
> -//===----------------------------------------------------------------------===//
> -// Other Lowering Hooks
> -//===----------------------------------------------------------------------===//
> -
> SDValue AMDGPUTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
> SDValue Chain = Op.getOperand(0);
> SDValue Cond = Op.getOperand(1);
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
--
Jan Vesely <jan.vesely at rutgers.edu>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20140615/034a3727/attachment.sig>
More information about the llvm-commits
mailing list