[llvm] r209421 - [mips] Use addiu in inline assembly tests since addi is not available in all ISA's
Daniel Sanders
daniel.sanders at imgtec.com
Thu May 22 04:46:58 PDT 2014
Author: dsanders
Date: Thu May 22 06:46:58 2014
New Revision: 209421
URL: http://llvm.org/viewvc/llvm-project?rev=209421&view=rev
Log:
[mips] Use addiu in inline assembly tests since addi is not available in all ISA's
Summary:
This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when
-integrated-as is enabled by default and we correctly detect the host CPU.
No functional change since these tests are testing the behaviour of the
constraint used for the third operand rather than the mnemonic.
Depends on D3842
Reviewers: zoran.jovanovic, jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3843
Modified:
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll
llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll?rev=209421&r1=209420&r2=209421&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll Thu May 22 06:46:58 2014
@@ -9,7 +9,7 @@ define i32 @main() nounwind {
entry:
;CHECK-ERRORS: error: invalid operand for inline asm constraint 'I'
- tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i32 7, i32 1048576) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 1048576) nounwind
ret i32 0
}
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll?rev=209421&r1=209420&r2=209421&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll Thu May 22 06:46:58 2014
@@ -10,7 +10,7 @@ entry:
;CHECK-ERRORS: error: invalid operand for inline asm constraint 'J'
- tail call i32 asm "addi $0,$1,$2", "=r,r,J"(i32 1024, i32 3) nounwind
+ tail call i32 asm "addiu $0,$1,$2", "=r,r,J"(i32 1024, i32 3) nounwind
ret i32 0
}
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll?rev=209421&r1=209420&r2=209421&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll Thu May 22 06:46:58 2014
@@ -10,7 +10,7 @@ entry:
;CHECK-ERRORS: error: invalid operand for inline asm constraint 'L'
- tail call i32 asm "addi $0,$1,$2", "=r,r,L"(i32 7, i32 1048579) nounwind
+ tail call i32 asm "addiu $0,$1,$2", "=r,r,L"(i32 7, i32 1048579) nounwind
ret i32 0
}
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll?rev=209421&r1=209420&r2=209421&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll Thu May 22 06:46:58 2014
@@ -11,7 +11,7 @@ entry:
;CHECK-ERRORS: error: invalid operand for inline asm constraint 'N'
- tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,N"(i32 7, i32 3) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 3) nounwind
ret i32 0
}
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll?rev=209421&r1=209420&r2=209421&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll Thu May 22 06:46:58 2014
@@ -11,6 +11,6 @@ entry:
;CHECK-ERRORS: error: invalid operand for inline asm constraint 'O'
- tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,O"(i32 undef, i32 16384) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 undef, i32 16384) nounwind
ret i32 0
}
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll?rev=209421&r1=209420&r2=209421&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll Thu May 22 06:46:58 2014
@@ -11,6 +11,6 @@ entry:
;CHECK-ERRORS: error: invalid operand for inline asm constraint 'P'
- tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,P"(i32 undef, i32 655536) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,P"(i32 undef, i32 655536) nounwind
ret i32 0
}
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll?rev=209421&r1=209420&r2=209421&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll Thu May 22 06:46:58 2014
@@ -7,27 +7,27 @@ entry:
; r with char
;CHECK: #APP
-;CHECK: addi ${{[0-9]+}},${{[0-9]+}},23
+;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},23
;CHECK: #NO_APP
- tail call i8 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i8 27, i8 23) nounwind
+ tail call i8 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i8 27, i8 23) nounwind
; r with short
;CHECK: #APP
-;CHECK: addi ${{[0-9]+}},${{[0-9]+}},13
+;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},13
;CHECK: #NO_APP
- tail call i16 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i16 17, i16 13) nounwind
+ tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i16 17, i16 13) nounwind
; r with int
;CHECK: #APP
-;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3
+;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3
;CHECK: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind
; Now c with 1024: make sure register $25 is picked
; CHECK: #APP
-; CHECK: addi $25,${{[0-9]+}},1024
+; CHECK: addiu $25,${{[0-9]+}},1024
; CHECK: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind
; Now l with 1024: make sure register lo is picked. We do this by checking the instruction
; after the inline expression for a mflo to pull the value out of lo.
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll?rev=209421&r1=209420&r2=209421&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll Thu May 22 06:46:58 2014
@@ -12,9 +12,9 @@ entry:
; r with long long
;CHECK: #APP
-;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3
+;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3
;CHECK: #NO_APP
- tail call i64 asm sideeffect "addi $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind
+ tail call i64 asm sideeffect "addiu $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind
ret i32 0
}
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll?rev=209421&r1=209420&r2=209421&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll Thu May 22 06:46:58 2014
@@ -12,9 +12,9 @@ define i32 @constraint_X() nounwind {
entry:
;CHECK_LITTLE_32-LABEL: constraint_X:
;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
+;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
;CHECK_LITTLE_32: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) ;
+ tail call i32 asm sideeffect "addiu $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@@ -23,9 +23,9 @@ define i32 @constraint_x() nounwind {
entry:
;CHECK_LITTLE_32-LABEL: constraint_x:
;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffd
+;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffd
;CHECK_LITTLE_32: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) ;
+ tail call i32 asm sideeffect "addiu $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@@ -34,9 +34,9 @@ define i32 @constraint_d() nounwind {
entry:
;CHECK_LITTLE_32-LABEL: constraint_d:
;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-3
+;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3
;CHECK_LITTLE_32: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) ;
+ tail call i32 asm sideeffect "addiu $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@@ -45,9 +45,9 @@ define i32 @constraint_m() nounwind {
entry:
;CHECK_LITTLE_32-LABEL: constraint_m:
;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-4
+;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-4
;CHECK_LITTLE_32: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) ;
+ tail call i32 asm sideeffect "addiu $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@@ -56,15 +56,15 @@ define i32 @constraint_z() nounwind {
entry:
;CHECK_LITTLE_32-LABEL: constraint_z:
;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-3
+;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3
;CHECK_LITTLE_32: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) ;
+ tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) ;
; z with 0
;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},$0
+;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},$0
;CHECK_LITTLE_32: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
ret i32 0
}
@@ -73,9 +73,9 @@ define i32 @constraint_longlong() nounwi
entry:
;CHECK_LITTLE_32-LABEL: constraint_longlong:
;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},3
+;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},3
;CHECK_LITTLE_32: #NO_APP
- tail call i64 asm sideeffect "addi $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
+ tail call i64 asm sideeffect "addiu $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
ret i32 0
}
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll?rev=209421&r1=209420&r2=209421&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll Thu May 22 06:46:58 2014
@@ -5,21 +5,21 @@ entry:
; First I with short
; CHECK: #APP
-; CHECK: addi ${{[0-9]+}},${{[0-9]+}},4096
+; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},4096
; CHECK: #NO_APP
- tail call i16 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind
+ tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind
; Then I with int
; CHECK: #APP
-; CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3
+; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
; CHECK: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind
; Now J with 0
; CHECK: #APP
-; CHECK: addi ${{[0-9]+}},${{[0-9]+}},0
+; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},0
; CHECK: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
; Now K with 64
; CHECK: #APP
@@ -35,21 +35,21 @@ entry:
; Now N with -3
; CHECK: #APP
-; CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3
+; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
; CHECK: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind
; Now O with -3
; CHECK: #APP
-; CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3
+; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
; CHECK: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwind
; Now P with 65535
; CHECK: #APP
-; CHECK: addi ${{[0-9]+}},${{[0-9]+}},65535
+; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},65535
; CHECK: #NO_APP
- tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind
; Now R Which takes the address of c
%c = alloca i32, align 4
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