[PATCH] [ARM64] Adds Cortex-A53 scheduling support for vector load/store post.

[Chad Rosier]

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Comment at: lib/Target/ARM64/ARM64InstrInfo.cpp:883
@@ +882,3 @@
+    break;
+  default:
+    break;
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I believe the usual convention is that the default case is at the top of the switch statement.

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Comment at: lib/Target/ARM64/ARM64InstrInfo.cpp:909
@@ +908,3 @@
+    break;
+  default:
+    break;
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Same.

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Comment at: test/CodeGen/ARM64/misched-basic-A53.ll:113
@@ +112,3 @@
+
+; Regression Test for Bug 19761
+; - [ARM64] Cortex-a53 schedule mode can't handle NEON post-increment load
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Lines 114-116 aren't necessary.  The git log should retain such history.

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Comment at: test/CodeGen/ARM64/misched-basic-A53.ll:119
@@ +118,3 @@
+define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
+  %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8* %A)
+  %tmp = getelementptr i8* %A, i32 32
----------------
You could add a CHECK-LABEL directive.

;  CHECK-LABEL: test_v16i8_post_imm_ld2

http://reviews.llvm.org/D3829