[PATCH] [ARM64] Adds Cortex-A53 scheduling support for vector load/store post.

[Dave Estes]

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Comment at: lib/Target/ARM64/ARM64SchedA53.td:221
@@ +220,3 @@
+def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
+def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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This set of post-increment instructions still has regex with the _POST as optional.

http://reviews.llvm.org/D3829