[PATCH][DAGCombiner] Split up an indexed load if only the base pointer value is live

Hal Finkel hfinkel at anl.gov
Mon May 12 12:35:02 PDT 2014


LGTM.

 -Hal

----- Original Message -----
> From: "Adam Nemet" <anemet at apple.com>
> To: "llvm-commits" <llvm-commits at cs.uiuc.edu>
> Sent: Monday, May 12, 2014 1:59:58 PM
> Subject: Re: [PATCH][DAGCombiner] Split up an indexed load if only the base	pointer value is live
> 
> 
> 
> Ping^2
> 
> On May 5, 2014, at 11:42 AM, Adam Nemet <anemet at apple.com> wrote:
> 
> > Ping.
> > 
> > + for (SDNode *U : N->uses())
> > + AddToWorkList(U);
> > 
> > For the review, please consider this written as:
> > AddUsersToWorkList(N)
> > 
> > On Apr 24, 2014, at 5:09 PM, Adam Nemet <anemet at apple.com> wrote:
> > 
> >> Right now the load may not get DCE'd because of the side-effect of
> >> updating
> >> the base pointer.
> >> 
> >> This can happen if we lower a read-modify-write of an illegal
> >> larger type
> >> (e.g. i48) such that the modification only affects one of the
> >> subparts (the
> >> lower i32 part but not the higher i16 part). See the testcase.
> >> 
> >> In order to spot the dead load we need to revisit it when
> >> SimplifyDemandedBits
> >> decided that the value of the load is masked off. This is the
> >> CommitTargetLoweringOpt piece.
> >> 
> >> I checked compile time with ARM64 by sending SPEC bitcode files
> >> through llc.
> >> No measurable change.
> >> 
> >> Fixes <rdar://problem/16031651>
> >> 
> >> Adam
> >> 
> 
> 
> >> 
> >> _______________________________________________
> >> llvm-commits mailing list
> >> llvm-commits at cs.uiuc.edu
> >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> > 
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> 
> 
> 
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-- 
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory



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