[PATCH] R600/SI: Cleanup parsing of register names.

[Matt Arsenault]

On Apr 14, 2014, at 12:44 AM, Christian König <deathsimple at vodafone.de> wrote:

>> +  // The low 7 bits encoding value is the register index, for both VGPRs and
>> +  // SGPRs.
>> +  unsigned RegIdx = MRI.getEncodingValue(reg) & 0x7;
> That doesn't looks valid on first glance. For the low 7 bis you want a mask of 0x1F here, not 0x7.
> 
> Christian.

You’re right. It also should be 8 bits, since VGPRs go to 255

> 
> Am 14.04.2014 08:51, schrieb Matt Arsenault:
>> Try to figure out the class and number of subregisters.
>> 
>> http://reviews.llvm.org/D3367
>> 
>> Files:
>>   lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
>>   lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
>> 
>> 
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