[PATCH] AArch64: big endian constant vector pools

[Christian Pirker]

  Hi Tim,

  your proposed patch is interesting, however does not fully address the issue.
  Please consider the following code (derived from the c-sample above):

    define void @foo( <4 x i64>* %loadaddr, <4 x i32>* %storeaddr ) {
      %1 = load <4 x i64>* %loadaddr
      %2 = add <4 x i64> %1, <i64 1, i64 2, i64 3, i64 4>
      %3 = trunc <4 x i64> %2 to <4 x i32>
      store <4 x i32> %3, <4 x i32>* %storeaddr
      ret void
    }

  compile with:
    llc -march aarch64_be -mattr neon

  Note that the const value is loaded with ldr q and used by vector instruction, thus swapping of the two upper and the two lower  vector elements. (I would like to note that D3345 does not help either, causing all vector elements swapped, but that's a different issue). I'm looking forward to your ideas.

  Thanks,
  Christian

http://reviews.llvm.org/D3305