[llvm] r205887 - [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.

[Bradley Smith]

Author: brasmi01
Date: Wed Apr  9 09:44:07 2014
New Revision: 205887

URL: http://llvm.org/viewvc/llvm-project?rev=205887&view=rev
Log:
[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.

Modified:
    llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt

Modified: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp?rev=205887&r1=205886&r2=205887&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp Wed Apr  9 09:44:07 2014
@@ -2001,7 +2001,7 @@ static DecodeStatus DecodeSIMDLdStSingle
     Inst.addOperand(MCOperand::CreateImm(index));
   }
 
-  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
+  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 
   switch (Inst.getOpcode()) {
   case ARM64::ST1i8_POST:
@@ -2162,7 +2162,7 @@ static DecodeStatus DecodeSIMDLdStSingle
   }
 
   Inst.addOperand(MCOperand::CreateImm(index));
-  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
+  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 
   switch (Inst.getOpcode()) {
   case ARM64::LD1i8_POST:

Modified: llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt?rev=205887&r1=205886&r2=205887&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt Wed Apr  9 09:44:07 2014
@@ -618,6 +618,7 @@
 0x0a 0x68 0x40 0x4c
 0x2d 0xac 0x40 0x0c
 0x4f 0x7c 0x40 0x4c
+0xe0 0x03 0x40 0x0d
 
 # CHECK: ld1.8b { v1 }, [x1]
 # CHECK: ld1.16b { v2, v3 }, [x2]
@@ -627,6 +628,7 @@
 # CHECK: ld1.4s { v10, v11, v12 }, [x0]
 # CHECK: ld1.1d { v13, v14 }, [x1]
 # CHECK: ld1.2d	{ v15 }, [x2]
+# CHECK: ld1.b	{ v0 }[0], [sp]
 
 0x41 0x70 0xdf 0x0c
 0x41 0xa0 0xdf 0x0c