[llvm] r205879 - [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.

[Bradley Smith]

Author: brasmi01
Date: Wed Apr  9 09:43:24 2014
New Revision: 205879

URL: http://llvm.org/viewvc/llvm-project?rev=205879&view=rev
Log:
[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td
    llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt

Modified: llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td?rev=205879&r1=205878&r2=205879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td Wed Apr  9 09:43:24 2014
@@ -1640,6 +1640,9 @@ multiclass BitfieldImm<bits<2> opc, stri
   def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
     let Inst{31} = 0;
     let Inst{22} = 0;
+    // imms<5> and immr<5> must be zero, else ReservedValue().
+    let Inst{21} = 0;
+    let Inst{15} = 0;
   }
   def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
     let Inst{31} = 1;
@@ -1671,6 +1674,9 @@ multiclass BitfieldImmWith2RegArgs<bits<
   def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
     let Inst{31} = 0;
     let Inst{22} = 0;
+    // imms<5> and immr<5> must be zero, else ReservedValue().
+    let Inst{21} = 0;
+    let Inst{15} = 0;
   }
   def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
     let Inst{31} = 1;

Modified: llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt?rev=205879&r1=205878&r2=205879&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt Wed Apr  9 09:43:24 2014
@@ -17,5 +17,7 @@
 # RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
 # RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
 
+# UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
+# RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
 
 # CHECK: invalid instruction encoding