[llvm] r205865 - [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.
Bradley Smith
bradley.smith at arm.com
Wed Apr 9 07:42:11 PDT 2014
Author: brasmi01
Date: Wed Apr 9 09:42:11 2014
New Revision: 205865
URL: http://llvm.org/viewvc/llvm-project?rev=205865&view=rev
Log:
[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.
Modified:
llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt
llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt
Modified: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp?rev=205865&r1=205864&r2=205865&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp Wed Apr 9 09:42:11 2014
@@ -854,6 +854,14 @@ static DecodeStatus DecodeThreeAddrSRegI
switch (Inst.getOpcode()) {
default:
return Fail;
+ case ARM64::ADDWrs:
+ case ARM64::ADDSWrs:
+ case ARM64::SUBWrs:
+ case ARM64::SUBSWrs:
+ // if shift == '11' then ReservedValue()
+ if (shiftHi == 0x3)
+ return Fail;
+ // Deliberate fallthrough
case ARM64::ANDWrs:
case ARM64::ANDSWrs:
case ARM64::BICWrs:
@@ -861,16 +869,23 @@ static DecodeStatus DecodeThreeAddrSRegI
case ARM64::ORRWrs:
case ARM64::ORNWrs:
case ARM64::EORWrs:
- case ARM64::EONWrs:
- case ARM64::ADDWrs:
- case ARM64::ADDSWrs:
- case ARM64::SUBWrs:
- case ARM64::SUBSWrs: {
+ case ARM64::EONWrs: {
+ // if sf == '0' and imm6<5> == '1' then ReservedValue()
+ if (shiftLo >> 5 == 1)
+ return Fail;
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break;
}
+ case ARM64::ADDXrs:
+ case ARM64::ADDSXrs:
+ case ARM64::SUBXrs:
+ case ARM64::SUBSXrs:
+ // if shift == '11' then ReservedValue()
+ if (shiftHi == 0x3)
+ return Fail;
+ // Deliberate fallthrough
case ARM64::ANDXrs:
case ARM64::ANDSXrs:
case ARM64::BICXrs:
@@ -879,10 +894,6 @@ static DecodeStatus DecodeThreeAddrSRegI
case ARM64::ORNXrs:
case ARM64::EORXrs:
case ARM64::EONXrs:
- case ARM64::ADDXrs:
- case ARM64::ADDSXrs:
- case ARM64::SUBXrs:
- case ARM64::SUBSXrs:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
Modified: llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt?rev=205865&r1=205864&r2=205865&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt Wed Apr 9 09:42:11 2014
@@ -85,72 +85,72 @@
0xac 0x01 0x0e 0x8b
0xac 0x31 0x0e 0x0b
0xac 0x31 0x0e 0x8b
-0xac 0xa9 0x4e 0x0b
-0xac 0xa9 0x4e 0x8b
-0xac 0x9d 0x8e 0x0b
+0xac 0x29 0x4e 0x0b
+0xac 0x29 0x4e 0x8b
+0xac 0x1d 0x8e 0x0b
0xac 0x9d 0x8e 0x8b
# CHECK: add w12, w13, w14
# CHECK: add x12, x13, x14
# CHECK: add w12, w13, w14, lsl #12
# CHECK: add x12, x13, x14, lsl #12
-# CHECK: add w12, w13, w14, lsr #42
-# CHECK: add x12, x13, x14, lsr #42
-# CHECK: add w12, w13, w14, asr #39
+# CHECK: add w12, w13, w14, lsr #10
+# CHECK: add x12, x13, x14, lsr #10
+# CHECK: add w12, w13, w14, asr #7
# CHECK: add x12, x13, x14, asr #39
0xac 0x01 0x0e 0x4b
0xac 0x01 0x0e 0xcb
0xac 0x31 0x0e 0x4b
0xac 0x31 0x0e 0xcb
-0xac 0xa9 0x4e 0x4b
-0xac 0xa9 0x4e 0xcb
-0xac 0x9d 0x8e 0x4b
+0xac 0x29 0x4e 0x4b
+0xac 0x29 0x4e 0xcb
+0xac 0x1d 0x8e 0x4b
0xac 0x9d 0x8e 0xcb
# CHECK: sub w12, w13, w14
# CHECK: sub x12, x13, x14
# CHECK: sub w12, w13, w14, lsl #12
# CHECK: sub x12, x13, x14, lsl #12
-# CHECK: sub w12, w13, w14, lsr #42
-# CHECK: sub x12, x13, x14, lsr #42
-# CHECK: sub w12, w13, w14, asr #39
+# CHECK: sub w12, w13, w14, lsr #10
+# CHECK: sub x12, x13, x14, lsr #10
+# CHECK: sub w12, w13, w14, asr #7
# CHECK: sub x12, x13, x14, asr #39
0xac 0x01 0x0e 0x2b
0xac 0x01 0x0e 0xab
0xac 0x31 0x0e 0x2b
0xac 0x31 0x0e 0xab
-0xac 0xa9 0x4e 0x2b
-0xac 0xa9 0x4e 0xab
-0xac 0x9d 0x8e 0x2b
+0xac 0x29 0x4e 0x2b
+0xac 0x29 0x4e 0xab
+0xac 0x1d 0x8e 0x2b
0xac 0x9d 0x8e 0xab
# CHECK: adds w12, w13, w14
# CHECK: adds x12, x13, x14
# CHECK: adds w12, w13, w14, lsl #12
# CHECK: adds x12, x13, x14, lsl #12
-# CHECK: adds w12, w13, w14, lsr #42
-# CHECK: adds x12, x13, x14, lsr #42
-# CHECK: adds w12, w13, w14, asr #39
+# CHECK: adds w12, w13, w14, lsr #10
+# CHECK: adds x12, x13, x14, lsr #10
+# CHECK: adds w12, w13, w14, asr #7
# CHECK: adds x12, x13, x14, asr #39
0xac 0x01 0x0e 0x6b
0xac 0x01 0x0e 0xeb
0xac 0x31 0x0e 0x6b
0xac 0x31 0x0e 0xeb
-0xac 0xa9 0x4e 0x6b
-0xac 0xa9 0x4e 0xeb
-0xac 0x9d 0x8e 0x6b
+0xac 0x29 0x4e 0x6b
+0xac 0x29 0x4e 0xeb
+0xac 0x1d 0x8e 0x6b
0xac 0x9d 0x8e 0xeb
# CHECK: subs w12, w13, w14
# CHECK: subs x12, x13, x14
# CHECK: subs w12, w13, w14, lsl #12
# CHECK: subs x12, x13, x14, lsl #12
-# CHECK: subs w12, w13, w14, lsr #42
-# CHECK: subs x12, x13, x14, lsr #42
-# CHECK: subs w12, w13, w14, asr #39
+# CHECK: subs w12, w13, w14, lsr #10
+# CHECK: subs x12, x13, x14, lsr #10
+# CHECK: subs w12, w13, w14, asr #7
# CHECK: subs x12, x13, x14, asr #39
#==---------------------------------------------------------------------------==
Modified: llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt?rev=205865&r1=205864&r2=205865&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt Wed Apr 9 09:42:11 2014
@@ -13,4 +13,9 @@
# MOVK with sf == 0 and hw<1> == 1 is unallocated.
# RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+# ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
+# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+
+
# CHECK: invalid instruction encoding
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