[PATCHTRAIN] ARM64 MC layer fixes
James Molloy
james at jamesmolloy.co.uk
Wed Apr 9 06:37:43 PDT 2014
Hi Tim (and other reviewers),
As discussed at Euro-LLVM and offline, we (Bradley and I) have been working
for a week on getting ARM's internal "MC Hammer" test suite passing on the
ARM64 backend. With the attached patches, ARM64 is fully correct when
comparing with our "golden reference" implementation, same as AArch64, with
the exception of:
* SXTB/UXTB will erroneously accept operands that are invalid. For
example, they will accept X registers when they shouldn't.
* A cyclone specific system register is not understood by our golden
reference.
We have done point fixes on a bunch of InstAliases, but actually we think
the alias logic should be refactored so that it is in one place instead of
4 (instprinter,asmparser,disassembler,tblgen).
I apologise that there are so many patches attached, but most are very
small. I've also attached a monolithic patch for your convenience. There
are a ton of small fixes and one fairly large refactor which brings over the
system register implementation from AArch64 to ARM64.
Patch list, in descending size order:
222K 0010-ARM64-Move-ARM64BaseInfo.-cpp-h-into-a-Utils-subdire.patch
73K 0009-ARM64-Copy-the-named-immediate-operand-mapping-logic.patch
44K 0011-ARM64-Switch-the-decoder-disassembler-instprinter-an.patch
24K 0013-ARM64-Remove-ARM64SYS.patch
21K 0027-ARM64-Rename-FP-to-the-UAL-compliant-X29.patch
14K 0019-ARM64-Add-missing-tlbi-operands-and-error-for-extra-.patch
14K 0018-ARM64-Rework-system-register-parsing-to-overcome-SPS.patch
12K 0028-ARM64-Rename-LR-to-the-UAL-compliant-X30.patch
11K 0021-ARM64-Floating-point-to-fixed-point-scaled-conversio.patch
10K 0031-ARM64-Fixup-ADR-ADRP-parsing-such-that-they-accept-i.patch
9.4K 0035-ARM64-When-printing-a-pre-indexed-address-with-0-the.patch
9.4K 0032-ARM64-Fix-canonicalisation-of-MOVs.-MOV-is-too-compl.patch
8.2K 0012-ARM64-Move-CPSRField-and-DBarrier-operands-over-to-A.patch
6.0K 0008-ARM64-Shifted-register-ALU-ops-are-reserved-if-sf-0-.patch
6.0K 0015-ARM64-Remove-PrefetchOp-and-use-ARM64PRFM-instead.patch
5.8K 0005-ARM64-Add-parsing-for-vector-lists-such-as-v0.8b-v3..patch
5.4K 0025-ARM64-SCVTF-and-FCVTZS-U-are-undefined-if-scale-5-0.patch
5.4K 0007-ARM64-Add-support-for-NV-condition-code-exists-only-.patch
4.8K 0017-ARM64-Port-over-the-PostEncoderMethod-from-AArch64-f.patch
4.3K 0039-ARM64-Properly-support-both-apple-and-standard-synta.patch
4.3K 0038-ARM64-Flag-setting-logical-add-sub-immediate-instruc.patch
4.1K 0042-ARM64-Change-SYS-without-a-register-to-an-alias-to-m.patch
3.9K 0004-ARM64-Correctly-alias-LSL-to-UXTW-for-32bit-instruct.patch
3.9K 0001-ARM64-Register-offset-loads-and-stores-with-the-opti.patch
3.8K 0014-ARM64-Add-WZR-to-isGPR32Register-since-every-use-nee.patch
3.2K 0029-ARM64-Tighten-up-the-special-casing-in-emitting-arit.patch
3.0K 0020-ARM64-Port-over-the-PostEncoderMethod-fix-for-SMULH-.patch
2.9K 0034-ARM64-Add-missing-shifted-register-MVN-alias-to-ORN.patch
2.8K 0026-ARM64-Add-a-PostEncoderMethod-to-FCMP-the-Rm-field-s.patch
2.6K 0002-ARM64-MOVK-with-sf-0-and-hw-1-1-is-unallocated.-Shif.patch
2.3K 0036-ARM64-Fix-disassembly-logic-for-extended-loads-store.patch
2.1K 0006-ARM64-Add-missing-1Q-1q-vector-kind-alias.patch
2.1K 0022-ARM64-UBFM-BFM-is-undefined-on-w-registers-when-imms.patch
2.0K 0024-ARM64-EXT-and-EXTR-instructions-on-v8i8-and-W-regs-r.patch
1.9K 0030-ARM64-Ensure-sp-is-decoded-as-SP-not-XZR-in-LD1-inst.patch
1.8K 0041-ARM64-Correctly-disassemble-ISB-operand-as-ISB-not-D.patch
1.7K 0037-ARM64-Conditional-branches-must-always-print-their-c.patch
1.6K 0003-ARM64-STRHro-and-STRBro-were-not-being-decoded-at-al.patch
1.5K 0033-ARM64-SXTW-UXTW-are-only-valid-aliases-for-32-bit-op.patch
1.3K 0016-ARM64-Use-PStateMapper-to-ensure-that-MSRcpsr-operan.patch
834 0023-ARM64-Scaled-fixed-point-FCVTZSs-should-also-have-bi.patch
Cheers,
James (and Bradley)
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diff --git a/lib/Target/ARM64/ARM64.h b/lib/Target/ARM64/ARM64.h
index f2c5e60..debb900 100644
--- a/lib/Target/ARM64/ARM64.h
+++ b/lib/Target/ARM64/ARM64.h
@@ -15,7 +15,7 @@
#ifndef TARGET_ARM64_H
#define TARGET_ARM64_H
-#include "MCTargetDesc/ARM64BaseInfo.h"
+#include "Utils/ARM64BaseInfo.h"
#include "MCTargetDesc/ARM64MCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/DataTypes.h"
diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td
index 38406f8..ee82419 100644
--- a/lib/Target/ARM64/ARM64InstrFormats.td
+++ b/lib/Target/ARM64/ARM64InstrFormats.td
@@ -156,6 +156,7 @@ def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
def AdrpOperand : AsmOperandClass {
let Name = "AdrpLabel";
let ParserMethod = "tryParseAdrpLabel";
+ let DiagnosticType = "InvalidLabel";
}
def adrplabel : Operand<i64> {
let EncoderMethod = "getAdrLabelOpValue";
@@ -166,6 +167,7 @@ def adrplabel : Operand<i64> {
def AdrOperand : AsmOperandClass {
let Name = "AdrLabel";
let ParserMethod = "tryParseAdrLabel";
+ let DiagnosticType = "InvalidLabel";
}
def adrlabel : Operand<i64> {
let EncoderMethod = "getAdrLabelOpValue";
@@ -304,12 +306,12 @@ def movk_symbol_g0 : Operand<i32> {
def fixedpoint32 : Operand<i32> {
let EncoderMethod = "getFixedPointScaleOpValue";
- let DecoderMethod = "DecodeFixedPointScaleImm";
+ let DecoderMethod = "DecodeFixedPointScaleImm32";
let ParserMatchClass = Imm1_32Operand;
}
def fixedpoint64 : Operand<i64> {
let EncoderMethod = "getFixedPointScaleOpValue";
- let DecoderMethod = "DecodeFixedPointScaleImm";
+ let DecoderMethod = "DecodeFixedPointScaleImm64";
let ParserMatchClass = Imm1_64Operand;
}
@@ -697,19 +699,30 @@ class CRmSystemI<Operand crmtype, bits<3> opc, string asm>
let Inst{7-5} = opc;
}
-// MRS/MSR system instructions.
-def SystemRegisterOperand : AsmOperandClass {
- let Name = "SystemRegister";
- let ParserMethod = "tryParseSystemRegister";
+// MRS/MSR system instructions. These have different operand classes because
+// a different subset of registers can be accessed through each instruction.
+def MRSSystemRegisterOperand : AsmOperandClass {
+ let Name = "MRSSystemRegister";
+ let ParserMethod = "tryParseSysReg";
}
// concatenation of 1, op0, op1, CRn, CRm, op2. 16-bit immediate.
-def sysreg_op : Operand<i32> {
- let ParserMatchClass = SystemRegisterOperand;
- let DecoderMethod = "DecodeSystemRegister";
- let PrintMethod = "printSystemRegister";
+def mrs_sysreg_op : Operand<i32> {
+ let ParserMatchClass = MRSSystemRegisterOperand;
+ let DecoderMethod = "DecodeMRSSystemRegister";
+ let PrintMethod = "printMRSSystemRegister";
}
-class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins sysreg_op:$systemreg),
+def MSRSystemRegisterOperand : AsmOperandClass {
+ let Name = "MSRSystemRegister";
+ let ParserMethod = "tryParseSysReg";
+}
+def msr_sysreg_op : Operand<i32> {
+ let ParserMatchClass = MSRSystemRegisterOperand;
+ let DecoderMethod = "DecodeMSRSystemRegister";
+ let PrintMethod = "printMSRSystemRegister";
+}
+
+class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
"mrs", "\t$Rt, $systemreg"> {
bits<15> systemreg;
let Inst{20} = 1;
@@ -719,7 +732,7 @@ class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins sysreg_op:$systemreg),
// FIXME: Some of these def CPSR, others don't. Best way to model that?
// Explicitly modeling each of the system register as a register class
// would do it, but feels like overkill at this point.
-class MSRI : RtSystemI<0, (outs), (ins sysreg_op:$systemreg, GPR64:$Rt),
+class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
"msr", "\t$systemreg, $Rt"> {
bits<15> systemreg;
let Inst{20} = 1;
@@ -728,7 +741,7 @@ class MSRI : RtSystemI<0, (outs), (ins sysreg_op:$systemreg, GPR64:$Rt),
def SystemCPSRFieldOperand : AsmOperandClass {
let Name = "SystemCPSRField";
- let ParserMethod = "tryParseCPSRField";
+ let ParserMethod = "tryParseSysReg";
}
def cpsrfield_op : Operand<i32> {
let ParserMatchClass = SystemCPSRFieldOperand;
@@ -761,22 +774,6 @@ def sys_cr_op : Operand<i32> {
let ParserMatchClass = SysCRAsmOperand;
}
-class SystemI<bit L, string asm>
- : SimpleSystemI<L,
- (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
- asm, "\t$op1, $Cn, $Cm, $op2">,
- Sched<[WriteSys]> {
- bits<3> op1;
- bits<4> Cn;
- bits<4> Cm;
- bits<3> op2;
- let Inst{20-19} = 0b01;
- let Inst{18-16} = op1;
- let Inst{15-12} = Cn;
- let Inst{11-8} = Cm;
- let Inst{7-5} = op2;
-}
-
class SystemXtI<bit L, string asm>
: RtSystemI<L, (outs),
(ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
@@ -1189,9 +1186,13 @@ class MulHi<bits<3> opc, string asm, SDNode OpNode>
let Inst{31-24} = 0b10011011;
let Inst{23-21} = opc;
let Inst{20-16} = Rm;
- let Inst{15-10} = 0b011111;
+ let Inst{15} = 0;
let Inst{9-5} = Rn;
let Inst{4-0} = Rd;
+
+ // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
+ // (i.e. all bits 1) but is ignored by the processor.
+ let PostEncoderMethod = "fixMulHigh";
}
class MulAccumWAlias<string asm, Instruction inst>
@@ -1588,6 +1589,8 @@ multiclass ExtractImm<string asm> {
(ARM64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
let Inst{31} = 0;
let Inst{22} = 0;
+ // imm<5> must be zero.
+ let imm{5} = 0;
}
def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
[(set GPR64:$Rd,
@@ -1625,6 +1628,9 @@ multiclass BitfieldImm<bits<2> opc, string asm> {
def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
let Inst{31} = 0;
let Inst{22} = 0;
+ // imms<5> and immr<5> must be zero, else ReservedValue().
+ let Inst{21} = 0;
+ let Inst{15} = 0;
}
def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
let Inst{31} = 1;
@@ -1656,6 +1662,9 @@ multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
let Inst{31} = 0;
let Inst{22} = 0;
+ // imms<5> and immr<5> must be zero, else ReservedValue().
+ let Inst{21} = 0;
+ let Inst{15} = 0;
}
def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
let Inst{31} = 1;
@@ -2406,7 +2415,13 @@ class am_unscaled_operand : Operand<i64> {
let ParserMatchClass = MemoryUnscaledOperand;
let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
}
+class am_unscaled_wb_operand : Operand<i64> {
+ let PrintMethod = "printAMUnscaledWB";
+ let ParserMatchClass = MemoryUnscaledOperand;
+ let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
+}
def am_unscaled : am_unscaled_operand;
+def am_unscaled_wb: am_unscaled_wb_operand;
def am_unscaled8 : am_unscaled_operand,
ComplexPattern<i64, 2, "SelectAddrModeUnscaled8", []>;
def am_unscaled16 : am_unscaled_operand,
@@ -2544,7 +2559,7 @@ class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
string asm>
: BaseLoadStorePreIdx<sz, V, opc,
(outs regtype:$Rt/*, GPR64sp:$wback*/),
- (ins am_unscaled:$addr), asm, ""/*"$addr.base = $wback"*/>,
+ (ins am_unscaled_wb:$addr), asm, ""/*"$addr.base = $wback"*/>,
Sched<[WriteLD, WriteAdr]>;
let mayStore = 1, mayLoad = 0 in
@@ -2552,7 +2567,7 @@ class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
string asm>
: BaseLoadStorePreIdx<sz, V, opc,
(outs/* GPR64sp:$wback*/),
- (ins regtype:$Rt, am_unscaled:$addr),
+ (ins regtype:$Rt, am_unscaled_wb:$addr),
asm, ""/*"$addr.base = $wback"*/>,
Sched<[WriteAdr, WriteST]>;
} // hasSideEffects = 0
@@ -2727,6 +2742,11 @@ def am_indexed32simm7 : Operand<i32> { // ComplexPattern<...>
let ParserMatchClass = MemoryIndexed32SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
+def am_indexed32simm7_wb : Operand<i32> { // ComplexPattern<...>
+ let PrintMethod = "printAMIndexed32WB";
+ let ParserMatchClass = MemoryIndexed32SImm7;
+ let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
+}
def MemoryIndexed64SImm7 : AsmOperandClass {
let Name = "MemoryIndexed64SImm7";
@@ -2737,6 +2757,11 @@ def am_indexed64simm7 : Operand<i32> { // ComplexPattern<...>
let ParserMatchClass = MemoryIndexed64SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
+def am_indexed64simm7_wb : Operand<i32> { // ComplexPattern<...>
+ let PrintMethod = "printAMIndexed64WB";
+ let ParserMatchClass = MemoryIndexed64SImm7;
+ let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
+}
def MemoryIndexed128SImm7 : AsmOperandClass {
let Name = "MemoryIndexed128SImm7";
@@ -2747,6 +2772,11 @@ def am_indexed128simm7 : Operand<i32> { // ComplexPattern<...>
let ParserMatchClass = MemoryIndexed128SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
+def am_indexed128simm7_wb : Operand<i32> { // ComplexPattern<...>
+ let PrintMethod = "printAMIndexed128WB";
+ let ParserMatchClass = MemoryIndexed128SImm7;
+ let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
+}
class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
string asm>
@@ -2886,6 +2916,18 @@ class StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
// True exclusive operations write to and/or read from the system's exclusive
// monitors, which as far as a compiler is concerned can be modelled as a
// random shared memory address. Hence LoadExclusive mayStore.
+//
+// Since these instructions have the undefined register bits set to 1 in
+// their canonical form, we need a post encoder method to set those bits
+// to 1 when encoding these instructions. We do this using the
+// fixLoadStoreExclusive function. This function has template parameters:
+//
+// fixLoadStoreExclusive<int hasRs, int hasRt2>
+//
+// hasRs indicates that the instruction uses the Rs field, so we won't set
+// it to 1 (and the same for Rt2). We don't need template parameters for
+// the other register fields since Rt and Rn are always used.
+//
let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
class BaseLoadStoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
dag oops, dag iops, string asm, string operands>
@@ -2906,10 +2948,10 @@ class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0,
: BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
bits<5> reg;
bits<5> base;
- let Inst{20-16} = 0b11111;
- let Inst{14-10} = 0b11111;
let Inst{9-5} = base;
let Inst{4-0} = reg;
+
+ let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
}
// Simple load acquires don't set the exclusive monitor
@@ -2936,10 +2978,11 @@ class LoadExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
bits<5> dst1;
bits<5> dst2;
bits<5> base;
- let Inst{20-16} = 0b11111;
let Inst{14-10} = dst2;
let Inst{9-5} = base;
let Inst{4-0} = dst1;
+
+ let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
}
// Simple store release operations do not check the exclusive monitor.
@@ -2962,11 +3005,11 @@ class StoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
bits<5> reg;
bits<5> base;
let Inst{20-16} = status;
- let Inst{14-10} = 0b11111;
let Inst{9-5} = base;
let Inst{4-0} = reg;
let Constraints = "@earlyclobber $Ws";
+ let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
}
class StoreExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
@@ -3016,7 +3059,7 @@ class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
Sched<[WriteFCvt]> {
bits<5> Rd;
bits<5> Rn;
- let Inst{30} = 0;
+ let Inst{30-29} = 0b00;
let Inst{28-24} = 0b11110;
let Inst{23-22} = type;
let Inst{21} = 1;
@@ -3037,7 +3080,7 @@ class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
bits<5> Rd;
bits<5> Rn;
bits<6> scale;
- let Inst{30} = 0;
+ let Inst{30-29} = 0b00;
let Inst{28-24} = 0b11110;
let Inst{23-22} = type;
let Inst{21} = 0;
@@ -3048,7 +3091,8 @@ class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
let Inst{4-0} = Rd;
}
-multiclass FPToInteger<bits<2> rmode, bits<3> opcode, string asm, SDPatternOperator OpN> {
+multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
+ SDPatternOperator OpN> {
// Unscaled single-precision to 32-bit
def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
[(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
@@ -3072,11 +3116,15 @@ multiclass FPToInteger<bits<2> rmode, bits<3> opcode, string asm, SDPatternOpera
[(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
let Inst{31} = 1; // 64-bit GPR flag
}
+}
+multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
+ SDPatternOperator OpN> {
// Scaled single-precision to 32-bit
def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
fixedpoint32, asm> {
let Inst{31} = 0; // 32-bit GPR flag
+ let scale{5} = 1;
}
// Scaled single-precision to 64-bit
@@ -3089,6 +3137,7 @@ multiclass FPToInteger<bits<2> rmode, bits<3> opcode, string asm, SDPatternOpera
def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
fixedpoint32, asm> {
let Inst{31} = 0; // 32-bit GPR flag
+ let scale{5} = 1;
}
// Scaled double-precision to 64-bit
@@ -3163,11 +3212,13 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDNode node> {
def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint32, asm> {
let Inst{31} = 0; // 32-bit GPR flag
let Inst{22} = 0; // 32-bit FPR flag
+ let scale{5} = 1;
}
def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint32, asm> {
let Inst{31} = 0; // 32-bit GPR flag
let Inst{22} = 1; // 64-bit FPR flag
+ let scale{5} = 1;
}
def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint64, asm> {
@@ -3210,8 +3261,10 @@ class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode,
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
- RegisterClass srcType, RegisterOperand dstType, string asm>
- : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd[1], $Rn", "", []>,
+ RegisterClass srcType, RegisterOperand dstType, string asm,
+ string kind>
+ : I<(outs dstType:$Rd), (ins srcType:$Rn), asm,
+ "{\t$Rd"#kind#"[1], $Rn|"#kind#"\t$Rd[1], $Rn}", "", []>,
Sched<[WriteFCopy]> {
bits<5> Rd;
bits<5> Rn;
@@ -3226,8 +3279,10 @@ class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode,
- RegisterOperand srcType, RegisterClass dstType, string asm>
- : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn[1]", "", []>,
+ RegisterOperand srcType, RegisterClass dstType, string asm,
+ string kind>
+ : I<(outs dstType:$Rd), (ins srcType:$Rn), asm,
+ "{\t$Rd, $Rn"#kind#"[1]|"#kind#"\t$Rd, $Rn[1]}", "", []>,
Sched<[WriteFCopy]> {
bits<5> Rd;
bits<5> Rn;
@@ -3264,21 +3319,16 @@ multiclass UnscaledConversion<string asm> {
}
def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
- asm#".d"> {
+ asm, ".d"> {
let Inst{31} = 1;
let Inst{22} = 0;
}
def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
- asm#".d"> {
+ asm, ".d"> {
let Inst{31} = 1;
let Inst{22} = 0;
}
-
- def : InstAlias<asm#"$Vd.d[1], $Rn",
- (!cast<Instruction>(NAME#XDHighr) V128:$Vd, GPR64:$Rn), 0>;
- def : InstAlias<asm#"$Rd, $Vn.d[1]",
- (!cast<Instruction>(NAME#DXHighr) GPR64:$Rd, V128:$Vn), 0>;
}
//---
@@ -3458,11 +3508,13 @@ class BaseOneOperandFPComparison<bit signalAllNans,
let Inst{31-23} = 0b000111100;
let Inst{21} = 1;
- let Inst{20-16} = 0b00000;
let Inst{15-10} = 0b001000;
let Inst{9-5} = Rn;
let Inst{4} = signalAllNans;
let Inst{3-0} = 0b1000;
+
+ // Rm should be 0b00000 canonically, but we need to accept any value.
+ let PostEncoderMethod = "fixOneOperandFPComparison";
}
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
@@ -4811,7 +4863,9 @@ class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
multiclass SIMDBitwiseExtract<string asm> {
- def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b">;
+ def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
+ let imm{3} = 0;
+ }
def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
}
@@ -8187,7 +8241,9 @@ def : TokenAlias<".16B", ".16b">;
def : TokenAlias<".8H", ".8h">;
def : TokenAlias<".4S", ".4s">;
def : TokenAlias<".2D", ".2d">;
+def : TokenAlias<".1Q", ".1q">;
def : TokenAlias<".B", ".b">;
def : TokenAlias<".H", ".h">;
def : TokenAlias<".S", ".s">;
def : TokenAlias<".D", ".d">;
+def : TokenAlias<".Q", ".q">;
diff --git a/lib/Target/ARM64/ARM64InstrInfo.td b/lib/Target/ARM64/ARM64InstrInfo.td
index 71910a6..66089d4 100644
--- a/lib/Target/ARM64/ARM64InstrInfo.td
+++ b/lib/Target/ARM64/ARM64InstrInfo.td
@@ -332,10 +332,13 @@ def MSRcpsr: MSRcpsrI;
def : Pat<(ARM64threadpointer), (MRS 0xde82)>;
// Generic system instructions
-def SYS : SystemI<0, "sys">;
def SYSxt : SystemXtI<0, "sys">;
def SYSLxt : SystemLXtI<1, "sysl">;
+def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
+ (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
+ sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
+
//===----------------------------------------------------------------------===//
// Move immediate instructions.
//===----------------------------------------------------------------------===//
@@ -604,13 +607,6 @@ defm ORN : LogicalReg<0b01, 1, "orn",
BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
defm ORR : LogicalReg<0b01, 0, "orr", or>;
-def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
-def : InstAlias<"mov $dst, $src",
- (ADDWri GPR32sp:$dst, GPR32sp:$src, 0, 0)>;
-def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
-def : InstAlias<"mov $dst, $src",
- (ADDXri GPR64sp:$dst, GPR64sp:$src, 0, 0)>;
-
def : InstAlias<"tst $src1, $src2",
(ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
def : InstAlias<"tst $src1, $src2",
@@ -631,6 +627,11 @@ def : InstAlias<"mvn $Wd, $Wm",
def : InstAlias<"mvn $Xd, $Xm",
(ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
+def : InstAlias<"mvn $Wd, $Wm, $sh",
+ (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift:$sh)>;
+def : InstAlias<"mvn $Xd, $Xm, $sh",
+ (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift:$sh)>;
+
def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
@@ -758,10 +759,7 @@ def : InstAlias<"asr $dst, $src, $shift",
def : InstAlias<"asr $dst, $src, $shift",
(SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
-def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
-def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
-def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
(UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
@@ -773,10 +771,7 @@ def : InstAlias<"lsr $dst, $src, $shift",
def : InstAlias<"lsr $dst, $src, $shift",
(UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
-def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
-def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
-def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
//===----------------------------------------------------------------------===//
// Conditionally set flags instructions.
@@ -967,13 +962,13 @@ def LDPQi : LoadPairOffset<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
def LDPSWi : LoadPairOffset<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
// Pair (pre-indexed)
-def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7, "ldp">;
-def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7, "ldp">;
-def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7, "ldp">;
-def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7, "ldp">;
-def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
+def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "ldp">;
+def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "ldp">;
+def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "ldp">;
+def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "ldp">;
+def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "ldp">;
-def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
+def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7_wb, "ldpsw">;
// Pair (post-indexed)
def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
@@ -1516,11 +1511,11 @@ def STPDi : StorePairOffset<0b01, 1, FPR64, am_indexed64simm7, "stp">;
def STPQi : StorePairOffset<0b10, 1, FPR128, am_indexed128simm7, "stp">;
// Pair (pre-indexed)
-def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7, "stp">;
-def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7, "stp">;
-def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7, "stp">;
-def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7, "stp">;
-def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7, "stp">;
+def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "stp">;
+def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "stp">;
+def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "stp">;
+def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "stp">;
+def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "stp">;
// Pair (pre-indexed)
def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
@@ -1859,19 +1854,23 @@ def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
// Scaled floating point to integer conversion instructions.
//===----------------------------------------------------------------------===//
-defm FCVTAS : FPToInteger<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
-defm FCVTAU : FPToInteger<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
-defm FCVTMS : FPToInteger<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
-defm FCVTMU : FPToInteger<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
-defm FCVTNS : FPToInteger<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
-defm FCVTNU : FPToInteger<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
-defm FCVTPS : FPToInteger<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
-defm FCVTPU : FPToInteger<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
-defm FCVTZS : FPToInteger<0b11, 0b000, "fcvtzs", fp_to_sint>;
-defm FCVTZU : FPToInteger<0b11, 0b001, "fcvtzu", fp_to_uint>;
+defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
+defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
+defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
+defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
+defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
+defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
+defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
+defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
+defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
+defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
+defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
+defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
let isCodeGenOnly = 1 in {
-defm FCVTZS_Int : FPToInteger<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
-defm FCVTZU_Int : FPToInteger<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
+defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
+defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
+defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
+defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
}
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/ARM64/ARM64MCInstLower.cpp b/lib/Target/ARM64/ARM64MCInstLower.cpp
index 01dc229..525f484 100644
--- a/lib/Target/ARM64/ARM64MCInstLower.cpp
+++ b/lib/Target/ARM64/ARM64MCInstLower.cpp
@@ -13,8 +13,8 @@
//===----------------------------------------------------------------------===//
#include "ARM64MCInstLower.h"
-#include "MCTargetDesc/ARM64BaseInfo.h"
#include "MCTargetDesc/ARM64MCExpr.h"
+#include "Utils/ARM64BaseInfo.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
diff --git a/lib/Target/ARM64/ARM64RegisterInfo.td b/lib/Target/ARM64/ARM64RegisterInfo.td
index 96001c5..5f50935 100644
--- a/lib/Target/ARM64/ARM64RegisterInfo.td
+++ b/lib/Target/ARM64/ARM64RegisterInfo.td
@@ -112,8 +112,8 @@ def X25 : ARM64Reg<25, "x25", [W25]>, DwarfRegAlias<W25>;
def X26 : ARM64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>;
def X27 : ARM64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>;
def X28 : ARM64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>;
-def FP : ARM64Reg<29, "fp", [W29]>, DwarfRegAlias<W29>;
-def LR : ARM64Reg<30, "lr", [W30]>, DwarfRegAlias<W30>;
+def FP : ARM64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>;
+def LR : ARM64Reg<30, "x30", [W30]>, DwarfRegAlias<W30>;
def SP : ARM64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>;
def XZR : ARM64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
}
diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index 38a61d8..e500579 100644
--- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -8,8 +8,8 @@
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/ARM64AddressingModes.h"
-#include "MCTargetDesc/ARM64BaseInfo.h"
#include "MCTargetDesc/ARM64MCExpr.h"
+#include "Utils/ARM64BaseInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
@@ -55,7 +55,7 @@ private:
unsigned parseCondCodeString(StringRef Cond);
bool parseCondCode(OperandVector &Operands, bool invertCondCode);
int tryParseRegister();
- int tryMatchVectorRegister(StringRef &Kind);
+ int tryMatchVectorRegister(StringRef &Kind, bool expected);
bool parseOptionalShift(OperandVector &Operands);
bool parseOptionalExtend(OperandVector &Operands);
bool parseRegister(OperandVector &Operands);
@@ -88,8 +88,8 @@ private:
OperandMatchResultTy tryParseNoIndexMemory(OperandVector &Operands);
OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
- OperandMatchResultTy tryParseSystemRegister(OperandVector &Operands);
- OperandMatchResultTy tryParseCPSRField(OperandVector &Operands);
+ OperandMatchResultTy tryParseMRSSystemRegister(OperandVector &Operands);
+ OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
OperandMatchResultTy tryParseSysCROperand(OperandVector &Operands);
OperandMatchResultTy tryParsePrefetch(OperandVector &Operands);
OperandMatchResultTy tryParseAdrpLabel(OperandVector &Operands);
@@ -141,14 +141,13 @@ private:
k_VectorList,
k_VectorIndex,
k_Token,
+ k_SysReg,
k_SysCR,
k_Prefetch,
k_Shifter,
k_Extend,
k_FPImm,
- k_Barrier,
- k_SystemRegister,
- k_CPSRField
+ k_Barrier
} Kind;
SMLoc StartLoc, EndLoc, OffsetLoc;
@@ -187,14 +186,9 @@ private:
unsigned Val; // Not the enum since not all values have names.
};
- struct SystemRegisterOp {
- // 16-bit immediate, usually from the ARM64SYS::SystermRegister enum,
- // but not limited to those values.
- uint16_t Val;
- };
-
- struct CPSRFieldOp {
- ARM64SYS::CPSRField Field;
+ struct SysRegOp {
+ const char *Data;
+ unsigned Length;
};
struct SysCRImmOp {
@@ -231,8 +225,7 @@ private:
struct ImmOp Imm;
struct FPImmOp FPImm;
struct BarrierOp Barrier;
- struct SystemRegisterOp SystemRegister;
- struct CPSRFieldOp CPSRField;
+ struct SysRegOp SysReg;
struct SysCRImmOp SysCRImm;
struct PrefetchOp Prefetch;
struct ShifterOp Shifter;
@@ -265,12 +258,6 @@ public:
case k_Barrier:
Barrier = o.Barrier;
break;
- case k_SystemRegister:
- SystemRegister = o.SystemRegister;
- break;
- case k_CPSRField:
- CPSRField = o.CPSRField;
- break;
case k_Register:
Reg = o.Reg;
break;
@@ -280,6 +267,9 @@ public:
case k_VectorIndex:
VectorIndex = o.VectorIndex;
break;
+ case k_SysReg:
+ SysReg = o.SysReg;
+ break;
case k_SysCR:
SysCRImm = o.SysCRImm;
break;
@@ -330,16 +320,6 @@ public:
return Barrier.Val;
}
- uint16_t getSystemRegister() const {
- assert(Kind == k_SystemRegister && "Invalid access!");
- return SystemRegister.Val;
- }
-
- ARM64SYS::CPSRField getCPSRField() const {
- assert(Kind == k_CPSRField && "Invalid access!");
- return CPSRField.Field;
- }
-
unsigned getReg() const {
assert(Kind == k_Register && "Invalid access!");
return Reg.RegNum;
@@ -360,6 +340,11 @@ public:
return VectorIndex.Val;
}
+ StringRef getSysReg() const {
+ assert(Kind == k_SysReg && "Invalid access!");
+ return StringRef(SysReg.Data, SysReg.Length);
+ }
+
unsigned getSysCR() const {
assert(Kind == k_SysCR && "Invalid access!");
return SysCRImm.Val;
@@ -664,14 +649,31 @@ public:
bool isFPImm() const { return Kind == k_FPImm; }
bool isBarrier() const { return Kind == k_Barrier; }
- bool isSystemRegister() const {
- if (Kind == k_SystemRegister)
- return true;
- // SPSel is legal for both the system register and the CPSR-field
- // variants of MSR, so special case that. Fugly.
- return (Kind == k_CPSRField && getCPSRField() == ARM64SYS::cpsr_SPSel);
+ bool isSysReg() const { return Kind == k_SysReg; }
+ bool isMRSSystemRegister() const {
+ if (!isSysReg()) return false;
+
+ bool IsKnownRegister;
+ ARM64SysReg::MRSMapper().fromString(getSysReg(), IsKnownRegister);
+
+ return IsKnownRegister;
+ }
+ bool isMSRSystemRegister() const {
+ if (!isSysReg()) return false;
+
+ bool IsKnownRegister;
+ ARM64SysReg::MSRMapper().fromString(getSysReg(), IsKnownRegister);
+
+ return IsKnownRegister;
+ }
+ bool isSystemCPSRField() const {
+ if (!isSysReg()) return false;
+
+ bool IsKnownRegister;
+ ARM64PState::PStateMapper().fromString(getSysReg(), IsKnownRegister);
+
+ return IsKnownRegister;
}
- bool isSystemCPSRField() const { return Kind == k_CPSRField; }
bool isReg() const { return Kind == k_Register && !Reg.isVector; }
bool isVectorReg() const { return Kind == k_Register && Reg.isVector; }
@@ -714,7 +716,7 @@ public:
bool isPrefetch() const { return Kind == k_Prefetch; }
bool isShifter() const { return Kind == k_Shifter; }
bool isExtend() const {
- // lsl is an alias for UXTX but will be a parsed as a k_Shifter operand.
+ // lsl is an alias for UXTW but will be a parsed as a k_Shifter operand.
if (isShifter()) {
ARM64_AM::ShiftType ST = ARM64_AM::getShiftType(Shifter.Val);
return ST == ARM64_AM::LSL;
@@ -997,13 +999,33 @@ public:
bool isAdrpLabel() const {
// Validation was handled during parsing, so we just sanity check that
// something didn't go haywire.
- return isImm();
+ if (!isImm())
+ return false;
+
+ if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
+ int64_t Val = CE->getValue();
+ int64_t Min = - (4096 * (1LL << (21 - 1)));
+ int64_t Max = 4096 * ((1LL << (21 - 1)) - 1);
+ return (Val % 4096) == 0 && Val >= Min && Val <= Max;
+ }
+
+ return true;
}
bool isAdrLabel() const {
// Validation was handled during parsing, so we just sanity check that
// something didn't go haywire.
- return isImm();
+ if (!isImm())
+ return false;
+
+ if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
+ int64_t Val = CE->getValue();
+ int64_t Min = - (1LL << (21 - 1));
+ int64_t Max = ((1LL << (21 - 1)) - 1);
+ return Val >= Min && Val <= Max;
+ }
+
+ return true;
}
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
@@ -1077,7 +1099,12 @@ public:
}
void addAdrpLabelOperands(MCInst &Inst, unsigned N) const {
- addImmOperands(Inst, N);
+ assert(N == 1 && "Invalid number of operands!");
+ const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
+ if (!MCE)
+ addExpr(Inst, getImm());
+ else
+ Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 12));
}
void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
@@ -1279,19 +1306,31 @@ public:
Inst.addOperand(MCOperand::CreateImm(getBarrier()));
}
- void addSystemRegisterOperands(MCInst &Inst, unsigned N) const {
+ void addMRSSystemRegisterOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- if (Kind == k_SystemRegister)
- Inst.addOperand(MCOperand::CreateImm(getSystemRegister()));
- else {
- assert(Kind == k_CPSRField && getCPSRField() == ARM64SYS::cpsr_SPSel);
- Inst.addOperand(MCOperand::CreateImm(ARM64SYS::SPSel));
- }
+
+ bool Valid;
+ uint32_t Bits = ARM64SysReg::MRSMapper().fromString(getSysReg(), Valid);
+
+ Inst.addOperand(MCOperand::CreateImm(Bits));
+ }
+
+ void addMSRSystemRegisterOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+
+ bool Valid;
+ uint32_t Bits = ARM64SysReg::MSRMapper().fromString(getSysReg(), Valid);
+
+ Inst.addOperand(MCOperand::CreateImm(Bits));
}
void addSystemCPSRFieldOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getCPSRField()));
+
+ bool Valid;
+ uint32_t Bits = ARM64PState::PStateMapper().fromString(getSysReg(), Valid);
+
+ Inst.addOperand(MCOperand::CreateImm(Bits));
}
void addSysCROperands(MCInst &Inst, unsigned N) const {
@@ -1346,10 +1385,10 @@ public:
void addExtendOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- // lsl is an alias for UXTX but will be a parsed as a k_Shifter operand.
+ // lsl is an alias for UXTW but will be a parsed as a k_Shifter operand.
if (isShifter()) {
assert(ARM64_AM::getShiftType(getShifter()) == ARM64_AM::LSL);
- unsigned imm = getArithExtendImm(ARM64_AM::UXTX,
+ unsigned imm = getArithExtendImm(ARM64_AM::UXTW,
ARM64_AM::getShiftValue(getShifter()));
Inst.addOperand(MCOperand::CreateImm(imm));
} else
@@ -1605,19 +1644,10 @@ public:
return Op;
}
- static ARM64Operand *CreateSystemRegister(uint16_t Val, SMLoc S,
- MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_SystemRegister, Ctx);
- Op->SystemRegister.Val = Val;
- Op->StartLoc = S;
- Op->EndLoc = S;
- return Op;
- }
-
- static ARM64Operand *CreateCPSRField(ARM64SYS::CPSRField Field, SMLoc S,
- MCContext &Ctx) {
- ARM64Operand *Op = new ARM64Operand(k_CPSRField, Ctx);
- Op->CPSRField.Field = Field;
+ static ARM64Operand *CreateSysReg(StringRef Str, SMLoc S, MCContext &Ctx) {
+ ARM64Operand *Op = new ARM64Operand(k_SysReg, Ctx);
+ Op->SysReg.Data = Str.data();
+ Op->SysReg.Length = Str.size();
Op->StartLoc = S;
Op->EndLoc = S;
return Op;
@@ -1702,30 +1732,12 @@ void ARM64Operand::print(raw_ostream &OS) const {
<< ") >";
break;
case k_Barrier: {
- const char *Name =
- ARM64SYS::getBarrierOptName((ARM64SYS::BarrierOption)getBarrier());
- OS << "<barrier ";
- if (Name)
- OS << Name;
+ bool Valid;
+ StringRef Name = ARM64DB::DBarrierMapper().toString(getBarrier(), Valid);
+ if (Valid)
+ OS << "<barrier " << Name << ">";
else
- OS << getBarrier();
- OS << ">";
- break;
- }
- case k_SystemRegister: {
- const char *Name = ARM64SYS::getSystemRegisterName(
- (ARM64SYS::SystemRegister)getSystemRegister());
- OS << "<systemreg ";
- if (Name)
- OS << Name;
- else
- OS << "#" << getSystemRegister();
- OS << ">";
- break;
- }
- case k_CPSRField: {
- const char *Name = ARM64SYS::getCPSRFieldName(getCPSRField());
- OS << "<cpsrfield " << Name << ">";
+ OS << "<barrier invalid #" << getBarrier() << ">";
break;
}
case k_Immediate:
@@ -1748,20 +1760,24 @@ void ARM64Operand::print(raw_ostream &OS) const {
case k_VectorIndex:
OS << "<vectorindex " << getVectorIndex() << ">";
break;
+ case k_SysReg:
+ OS << "<sysreg: " << getSysReg() << '>';
+ break;
case k_Token:
OS << "'" << getToken() << "'";
break;
case k_SysCR:
OS << "c" << getSysCR();
break;
- case k_Prefetch:
- OS << "<prfop ";
- if (ARM64_AM::isNamedPrefetchOp(getPrefetch()))
- OS << ARM64_AM::getPrefetchOpName((ARM64_AM::PrefetchOp)getPrefetch());
+ case k_Prefetch: {
+ bool Valid;
+ StringRef Name = ARM64PRFM::PRFMMapper().toString(getPrefetch(), Valid);
+ if (Valid)
+ OS << "<prfop " << Name << ">";
else
- OS << "#" << getPrefetch();
- OS << ">";
+ OS << "<prfop invalid #" << getPrefetch() << ">";
break;
+ }
case k_Shifter: {
unsigned Val = getShifter();
OS << "<" << ARM64_AM::getShiftName(ARM64_AM::getShiftType(Val)) << " #"
@@ -1880,8 +1896,8 @@ int ARM64AsmParser::tryParseRegister() {
// Also handle a few aliases of registers.
if (RegNum == 0)
RegNum = StringSwitch<unsigned>(lowerCase)
- .Case("x29", ARM64::FP)
- .Case("x30", ARM64::LR)
+ .Case("fp", ARM64::FP)
+ .Case("lr", ARM64::LR)
.Case("x31", ARM64::XZR)
.Case("w31", ARM64::WZR)
.Default(0);
@@ -1895,7 +1911,7 @@ int ARM64AsmParser::tryParseRegister() {
/// tryMatchVectorRegister - Try to parse a vector register name with optional
/// kind specifier. If it is a register specifier, eat the token and return it.
-int ARM64AsmParser::tryMatchVectorRegister(StringRef &Kind) {
+int ARM64AsmParser::tryMatchVectorRegister(StringRef &Kind, bool expected) {
if (Parser.getTok().isNot(AsmToken::Identifier)) {
TokError("vector register expected");
return -1;
@@ -1918,6 +1934,9 @@ int ARM64AsmParser::tryMatchVectorRegister(StringRef &Kind) {
Parser.Lex(); // Eat the register token.
return RegNum;
}
+
+ if (expected)
+ TokError("vector register expected");
return -1;
}
@@ -2030,21 +2049,9 @@ ARM64AsmParser::tryParsePrefetch(OperandVector &Operands) {
return MatchOperand_ParseFail;
}
- unsigned prfop = StringSwitch<unsigned>(Tok.getString())
- .Case("pldl1keep", ARM64_AM::PLDL1KEEP)
- .Case("pldl1strm", ARM64_AM::PLDL1STRM)
- .Case("pldl2keep", ARM64_AM::PLDL2KEEP)
- .Case("pldl2strm", ARM64_AM::PLDL2STRM)
- .Case("pldl3keep", ARM64_AM::PLDL3KEEP)
- .Case("pldl3strm", ARM64_AM::PLDL3STRM)
- .Case("pstl1keep", ARM64_AM::PSTL1KEEP)
- .Case("pstl1strm", ARM64_AM::PSTL1STRM)
- .Case("pstl2keep", ARM64_AM::PSTL2KEEP)
- .Case("pstl2strm", ARM64_AM::PSTL2STRM)
- .Case("pstl3keep", ARM64_AM::PSTL3KEEP)
- .Case("pstl3strm", ARM64_AM::PSTL3STRM)
- .Default(0xff);
- if (prfop == 0xff) {
+ bool Valid;
+ unsigned prfop = ARM64PRFM::PRFMMapper().fromString(Tok.getString(), Valid);
+ if (!Valid) {
TokError("pre-fetch hint expected");
return MatchOperand_ParseFail;
}
@@ -2060,40 +2067,43 @@ ARM64AsmParser::OperandMatchResultTy
ARM64AsmParser::tryParseAdrpLabel(OperandVector &Operands) {
SMLoc S = getLoc();
const MCExpr *Expr;
+
+ if (Parser.getTok().is(AsmToken::Hash)) {
+ Parser.Lex(); // Eat hash token.
+ }
+
if (parseSymbolicImmVal(Expr))
return MatchOperand_ParseFail;
ARM64MCExpr::VariantKind ELFRefKind;
MCSymbolRefExpr::VariantKind DarwinRefKind;
const MCConstantExpr *Addend;
- if (!classifySymbolRef(Expr, ELFRefKind, DarwinRefKind, Addend)) {
- Error(S, "modified label reference + constant expected");
- return MatchOperand_ParseFail;
- }
-
- if (DarwinRefKind == MCSymbolRefExpr::VK_None &&
- ELFRefKind == ARM64MCExpr::VK_INVALID) {
- // No modifier was specified at all; this is the syntax for an ELF basic
- // ADRP relocation (unfortunately).
- Expr = ARM64MCExpr::Create(Expr, ARM64MCExpr::VK_ABS_PAGE, getContext());
- } else if ((DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGE ||
- DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGE) &&
- Addend != 0) {
- Error(S, "gotpage label reference not allowed an addend");
- return MatchOperand_ParseFail;
- } else if (DarwinRefKind != MCSymbolRefExpr::VK_PAGE &&
- DarwinRefKind != MCSymbolRefExpr::VK_GOTPAGE &&
- DarwinRefKind != MCSymbolRefExpr::VK_TLVPPAGE &&
- ELFRefKind != ARM64MCExpr::VK_GOT_PAGE &&
- ELFRefKind != ARM64MCExpr::VK_GOTTPREL_PAGE &&
- ELFRefKind != ARM64MCExpr::VK_TLSDESC_PAGE) {
- // The operand must be an @page or @gotpage qualified symbolref.
- Error(S, "page or gotpage label reference expected");
- return MatchOperand_ParseFail;
+ if (classifySymbolRef(Expr, ELFRefKind, DarwinRefKind, Addend)) {
+ if (DarwinRefKind == MCSymbolRefExpr::VK_None &&
+ ELFRefKind == ARM64MCExpr::VK_INVALID) {
+ // No modifier was specified at all; this is the syntax for an ELF basic
+ // ADRP relocation (unfortunately).
+ Expr = ARM64MCExpr::Create(Expr, ARM64MCExpr::VK_ABS_PAGE, getContext());
+ } else if ((DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGE ||
+ DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGE) &&
+ Addend != 0) {
+ Error(S, "gotpage label reference not allowed an addend");
+ return MatchOperand_ParseFail;
+ } else if (DarwinRefKind != MCSymbolRefExpr::VK_PAGE &&
+ DarwinRefKind != MCSymbolRefExpr::VK_GOTPAGE &&
+ DarwinRefKind != MCSymbolRefExpr::VK_TLVPPAGE &&
+ ELFRefKind != ARM64MCExpr::VK_GOT_PAGE &&
+ ELFRefKind != ARM64MCExpr::VK_GOTTPREL_PAGE &&
+ ELFRefKind != ARM64MCExpr::VK_TLSDESC_PAGE) {
+ // The operand must be an @page or @gotpage qualified symbolref.
+ Error(S, "page or gotpage label reference expected");
+ return MatchOperand_ParseFail;
+ }
}
- // We have a label reference possibly with addend. The addend is a raw value
- // here. The linker will adjust it to only reference the page.
+ // We have either a label reference possibly with addend or an immediate. The
+ // addend is a raw value here. The linker will adjust it to only reference the
+ // page.
SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
Operands.push_back(ARM64Operand::CreateImm(Expr, S, E, getContext()));
@@ -2106,20 +2116,14 @@ ARM64AsmParser::OperandMatchResultTy
ARM64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
SMLoc S = getLoc();
const MCExpr *Expr;
- if (getParser().parseExpression(Expr))
- return MatchOperand_ParseFail;
- // The operand must be an un-qualified assembler local symbolref.
- // FIXME: wrong for ELF.
- if (const MCSymbolRefExpr *SRE = dyn_cast<const MCSymbolRefExpr>(Expr)) {
- // FIXME: Should reference the MachineAsmInfo to get the private prefix.
- bool isTemporary = SRE->getSymbol().getName().startswith("L");
- if (!isTemporary || SRE->getKind() != MCSymbolRefExpr::VK_None) {
- Error(S, "unqualified, assembler-local label name expected");
- return MatchOperand_ParseFail;
- }
+ if (Parser.getTok().is(AsmToken::Hash)) {
+ Parser.Lex(); // Eat hash token.
}
+ if (getParser().parseExpression(Expr))
+ return MatchOperand_ParseFail;
+
SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
Operands.push_back(ARM64Operand::CreateImm(Expr, S, E, getContext()));
@@ -2185,7 +2189,7 @@ ARM64AsmParser::tryParseFPImm(OperandVector &Operands) {
/// parseCondCodeString - Parse a Condition Code string.
unsigned ARM64AsmParser::parseCondCodeString(StringRef Cond) {
- unsigned CC = StringSwitch<unsigned>(Cond)
+ unsigned CC = StringSwitch<unsigned>(Cond.lower())
.Case("eq", ARM64CC::EQ)
.Case("ne", ARM64CC::NE)
.Case("cs", ARM64CC::CS)
@@ -2203,25 +2207,8 @@ unsigned ARM64AsmParser::parseCondCodeString(StringRef Cond) {
.Case("gt", ARM64CC::GT)
.Case("le", ARM64CC::LE)
.Case("al", ARM64CC::AL)
- // Upper case works too. Not mixed case, though.
- .Case("EQ", ARM64CC::EQ)
- .Case("NE", ARM64CC::NE)
- .Case("CS", ARM64CC::CS)
- .Case("HS", ARM64CC::CS)
- .Case("CC", ARM64CC::CC)
- .Case("LO", ARM64CC::CC)
- .Case("MI", ARM64CC::MI)
- .Case("PL", ARM64CC::PL)
- .Case("VS", ARM64CC::VS)
- .Case("VC", ARM64CC::VC)
- .Case("HI", ARM64CC::HI)
- .Case("LS", ARM64CC::LS)
- .Case("GE", ARM64CC::GE)
- .Case("LT", ARM64CC::LT)
- .Case("GT", ARM64CC::GT)
- .Case("LE", ARM64CC::LE)
- .Case("AL", ARM64CC::AL)
- .Default(~0U);
+ .Case("nv", ARM64CC::NV)
+ .Default(ARM64CC::Invalid);
return CC;
}
@@ -2234,7 +2221,7 @@ bool ARM64AsmParser::parseCondCode(OperandVector &Operands,
StringRef Cond = Tok.getString();
unsigned CC = parseCondCodeString(Cond);
- if (CC == ~0U)
+ if (CC == ARM64CC::Invalid)
return TokError("invalid condition code");
Parser.Lex(); // Eat identifier token.
@@ -2551,6 +2538,12 @@ bool ARM64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
} else if (!Op.compare_lower("ipas2le1")) {
// SYS #4, C8, C4, #5
SYS_ALIAS(4, 8, 4, 5);
+ } else if (!Op.compare_lower("ipas2e1is")) {
+ // SYS #4, C8, C4, #1
+ SYS_ALIAS(4, 8, 0, 1);
+ } else if (!Op.compare_lower("ipas2le1is")) {
+ // SYS #4, C8, C4, #5
+ SYS_ALIAS(4, 8, 0, 5);
} else if (!Op.compare_lower("vmalls12e1")) {
// SYS #4, C8, C7, #6
SYS_ALIAS(4, 8, 7, 6);
@@ -2566,12 +2559,17 @@ bool ARM64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
Parser.Lex(); // Eat operand.
+ bool ExpectRegister = (Op.lower().find("all") == StringRef::npos);
+ bool HasRegister = false;
+
// Check for the optional register operand.
if (getLexer().is(AsmToken::Comma)) {
Parser.Lex(); // Eat comma.
if (Tok.isNot(AsmToken::Identifier) || parseRegister(Operands))
return TokError("expected register operand");
+
+ HasRegister = true;
}
if (getLexer().isNot(AsmToken::EndOfStatement)) {
@@ -2579,6 +2577,13 @@ bool ARM64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
return TokError("unexpected token in argument list");
}
+ if (ExpectRegister && !HasRegister) {
+ return TokError("specified " + Mnemonic + " op requires a register");
+ }
+ else if (!ExpectRegister && HasRegister) {
+ return TokError("specified " + Mnemonic + " op does not use a register");
+ }
+
Parser.Lex(); // Consume the EndOfStatement
return false;
}
@@ -2614,27 +2619,15 @@ ARM64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
return MatchOperand_ParseFail;
}
- unsigned Opt = StringSwitch<unsigned>(Tok.getString())
- .Case("oshld", ARM64SYS::OSHLD)
- .Case("oshst", ARM64SYS::OSHST)
- .Case("osh", ARM64SYS::OSH)
- .Case("nshld", ARM64SYS::NSHLD)
- .Case("nshst", ARM64SYS::NSHST)
- .Case("nsh", ARM64SYS::NSH)
- .Case("ishld", ARM64SYS::ISHLD)
- .Case("ishst", ARM64SYS::ISHST)
- .Case("ish", ARM64SYS::ISH)
- .Case("ld", ARM64SYS::LD)
- .Case("st", ARM64SYS::ST)
- .Case("sy", ARM64SYS::SY)
- .Default(ARM64SYS::InvalidBarrier);
- if (Opt == ARM64SYS::InvalidBarrier) {
+ bool Valid;
+ unsigned Opt = ARM64DB::DBarrierMapper().fromString(Tok.getString(), Valid);
+ if (!Valid) {
TokError("invalid barrier option name");
return MatchOperand_ParseFail;
}
// The only valid named option for ISB is 'sy'
- if (Mnemonic == "isb" && Opt != ARM64SYS::SY) {
+ if (Mnemonic == "isb" && Opt != ARM64DB::SY) {
TokError("'sy' or #imm operand expected");
return MatchOperand_ParseFail;
}
@@ -2646,352 +2639,15 @@ ARM64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
}
ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParseSystemRegister(OperandVector &Operands) {
- const AsmToken &Tok = Parser.getTok();
-
- // It can be specified as a symbolic name.
- if (Tok.isNot(AsmToken::Identifier))
- return MatchOperand_NoMatch;
-
- auto ID = Tok.getString().lower();
- ARM64SYS::SystemRegister Reg =
- StringSwitch<ARM64SYS::SystemRegister>(ID)
- .Case("spsr_el1", ARM64SYS::SPSR_svc)
- .Case("spsr_svc", ARM64SYS::SPSR_svc)
- .Case("elr_el1", ARM64SYS::ELR_EL1)
- .Case("sp_el0", ARM64SYS::SP_EL0)
- .Case("spsel", ARM64SYS::SPSel)
- .Case("daif", ARM64SYS::DAIF)
- .Case("currentel", ARM64SYS::CurrentEL)
- .Case("nzcv", ARM64SYS::NZCV)
- .Case("fpcr", ARM64SYS::FPCR)
- .Case("fpsr", ARM64SYS::FPSR)
- .Case("dspsr", ARM64SYS::DSPSR)
- .Case("dlr", ARM64SYS::DLR)
- .Case("spsr_el2", ARM64SYS::SPSR_hyp)
- .Case("spsr_hyp", ARM64SYS::SPSR_hyp)
- .Case("elr_el2", ARM64SYS::ELR_EL2)
- .Case("sp_el1", ARM64SYS::SP_EL1)
- .Case("spsr_irq", ARM64SYS::SPSR_irq)
- .Case("spsr_abt", ARM64SYS::SPSR_abt)
- .Case("spsr_und", ARM64SYS::SPSR_und)
- .Case("spsr_fiq", ARM64SYS::SPSR_fiq)
- .Case("spsr_el3", ARM64SYS::SPSR_EL3)
- .Case("elr_el3", ARM64SYS::ELR_EL3)
- .Case("sp_el2", ARM64SYS::SP_EL2)
- .Case("midr_el1", ARM64SYS::MIDR_EL1)
- .Case("ctr_el0", ARM64SYS::CTR_EL0)
- .Case("mpidr_el1", ARM64SYS::MPIDR_EL1)
- .Case("ecoidr_el1", ARM64SYS::ECOIDR_EL1)
- .Case("dczid_el0", ARM64SYS::DCZID_EL0)
- .Case("mvfr0_el1", ARM64SYS::MVFR0_EL1)
- .Case("mvfr1_el1", ARM64SYS::MVFR1_EL1)
- .Case("id_aa64pfr0_el1", ARM64SYS::ID_AA64PFR0_EL1)
- .Case("id_aa64pfr1_el1", ARM64SYS::ID_AA64PFR1_EL1)
- .Case("id_aa64dfr0_el1", ARM64SYS::ID_AA64DFR0_EL1)
- .Case("id_aa64dfr1_el1", ARM64SYS::ID_AA64DFR1_EL1)
- .Case("id_aa64isar0_el1", ARM64SYS::ID_AA64ISAR0_EL1)
- .Case("id_aa64isar1_el1", ARM64SYS::ID_AA64ISAR1_EL1)
- .Case("id_aa64mmfr0_el1", ARM64SYS::ID_AA64MMFR0_EL1)
- .Case("id_aa64mmfr1_el1", ARM64SYS::ID_AA64MMFR1_EL1)
- .Case("ccsidr_el1", ARM64SYS::CCSIDR_EL1)
- .Case("clidr_el1", ARM64SYS::CLIDR_EL1)
- .Case("aidr_el1", ARM64SYS::AIDR_EL1)
- .Case("csselr_el1", ARM64SYS::CSSELR_EL1)
- .Case("vpidr_el2", ARM64SYS::VPIDR_EL2)
- .Case("vmpidr_el2", ARM64SYS::VMPIDR_EL2)
- .Case("sctlr_el1", ARM64SYS::SCTLR_EL1)
- .Case("sctlr_el2", ARM64SYS::SCTLR_EL2)
- .Case("sctlr_el3", ARM64SYS::SCTLR_EL3)
- .Case("actlr_el1", ARM64SYS::ACTLR_EL1)
- .Case("actlr_el2", ARM64SYS::ACTLR_EL2)
- .Case("actlr_el3", ARM64SYS::ACTLR_EL3)
- .Case("cpacr_el1", ARM64SYS::CPACR_EL1)
- .Case("cptr_el2", ARM64SYS::CPTR_EL2)
- .Case("cptr_el3", ARM64SYS::CPTR_EL3)
- .Case("scr_el3", ARM64SYS::SCR_EL3)
- .Case("hcr_el2", ARM64SYS::HCR_EL2)
- .Case("mdcr_el2", ARM64SYS::MDCR_EL2)
- .Case("mdcr_el3", ARM64SYS::MDCR_EL3)
- .Case("hstr_el2", ARM64SYS::HSTR_EL2)
- .Case("hacr_el2", ARM64SYS::HACR_EL2)
- .Case("ttbr0_el1", ARM64SYS::TTBR0_EL1)
- .Case("ttbr1_el1", ARM64SYS::TTBR1_EL1)
- .Case("ttbr0_el2", ARM64SYS::TTBR0_EL2)
- .Case("ttbr0_el3", ARM64SYS::TTBR0_EL3)
- .Case("vttbr_el2", ARM64SYS::VTTBR_EL2)
- .Case("tcr_el1", ARM64SYS::TCR_EL1)
- .Case("tcr_el2", ARM64SYS::TCR_EL2)
- .Case("tcr_el3", ARM64SYS::TCR_EL3)
- .Case("vtcr_el2", ARM64SYS::VTCR_EL2)
- .Case("adfsr_el1", ARM64SYS::ADFSR_EL1)
- .Case("aifsr_el1", ARM64SYS::AIFSR_EL1)
- .Case("adfsr_el2", ARM64SYS::ADFSR_EL2)
- .Case("aifsr_el2", ARM64SYS::AIFSR_EL2)
- .Case("adfsr_el3", ARM64SYS::ADFSR_EL3)
- .Case("aifsr_el3", ARM64SYS::AIFSR_EL3)
- .Case("esr_el1", ARM64SYS::ESR_EL1)
- .Case("esr_el2", ARM64SYS::ESR_EL2)
- .Case("esr_el3", ARM64SYS::ESR_EL3)
- .Case("far_el1", ARM64SYS::FAR_EL1)
- .Case("far_el2", ARM64SYS::FAR_EL2)
- .Case("far_el3", ARM64SYS::FAR_EL3)
- .Case("hpfar_el2", ARM64SYS::HPFAR_EL2)
- .Case("par_el1", ARM64SYS::PAR_EL1)
- .Case("mair_el1", ARM64SYS::MAIR_EL1)
- .Case("mair_el2", ARM64SYS::MAIR_EL2)
- .Case("mair_el3", ARM64SYS::MAIR_EL3)
- .Case("amair_el1", ARM64SYS::AMAIR_EL1)
- .Case("amair_el2", ARM64SYS::AMAIR_EL2)
- .Case("amair_el3", ARM64SYS::AMAIR_EL3)
- .Case("vbar_el1", ARM64SYS::VBAR_EL1)
- .Case("vbar_el2", ARM64SYS::VBAR_EL2)
- .Case("vbar_el3", ARM64SYS::VBAR_EL3)
- .Case("rvbar_el1", ARM64SYS::RVBAR_EL1)
- .Case("rvbar_el2", ARM64SYS::RVBAR_EL2)
- .Case("rvbar_el3", ARM64SYS::RVBAR_EL3)
- .Case("isr_el1", ARM64SYS::ISR_EL1)
- .Case("contextidr_el1", ARM64SYS::CONTEXTIDR_EL1)
- .Case("tpidr_el0", ARM64SYS::TPIDR_EL0)
- .Case("tpidrro_el0", ARM64SYS::TPIDRRO_EL0)
- .Case("tpidr_el1", ARM64SYS::TPIDR_EL1)
- .Case("tpidr_el2", ARM64SYS::TPIDR_EL2)
- .Case("tpidr_el3", ARM64SYS::TPIDR_EL3)
- .Case("teecr32_el1", ARM64SYS::TEECR32_EL1)
- .Case("cntfrq_el0", ARM64SYS::CNTFRQ_EL0)
- .Case("cntpct_el0", ARM64SYS::CNTPCT_EL0)
- .Case("cntvct_el0", ARM64SYS::CNTVCT_EL0)
- .Case("cntvoff_el2", ARM64SYS::CNTVOFF_EL2)
- .Case("cntkctl_el1", ARM64SYS::CNTKCTL_EL1)
- .Case("cnthctl_el2", ARM64SYS::CNTHCTL_EL2)
- .Case("cntp_tval_el0", ARM64SYS::CNTP_TVAL_EL0)
- .Case("cntp_ctl_el0", ARM64SYS::CNTP_CTL_EL0)
- .Case("cntp_cval_el0", ARM64SYS::CNTP_CVAL_EL0)
- .Case("cntv_tval_el0", ARM64SYS::CNTV_TVAL_EL0)
- .Case("cntv_ctl_el0", ARM64SYS::CNTV_CTL_EL0)
- .Case("cntv_cval_el0", ARM64SYS::CNTV_CVAL_EL0)
- .Case("cnthp_tval_el2", ARM64SYS::CNTHP_TVAL_EL2)
- .Case("cnthp_ctl_el2", ARM64SYS::CNTHP_CTL_EL2)
- .Case("cnthp_cval_el2", ARM64SYS::CNTHP_CVAL_EL2)
- .Case("cntps_tval_el1", ARM64SYS::CNTPS_TVAL_EL1)
- .Case("cntps_ctl_el1", ARM64SYS::CNTPS_CTL_EL1)
- .Case("cntps_cval_el1", ARM64SYS::CNTPS_CVAL_EL1)
- .Case("dacr32_el2", ARM64SYS::DACR32_EL2)
- .Case("ifsr32_el2", ARM64SYS::IFSR32_EL2)
- .Case("teehbr32_el1", ARM64SYS::TEEHBR32_EL1)
- .Case("sder32_el3", ARM64SYS::SDER32_EL3)
- .Case("fpexc32_el2", ARM64SYS::FPEXC32_EL2)
- .Case("current_el", ARM64SYS::CurrentEL)
- .Case("pmevcntr0_el0", ARM64SYS::PMEVCNTR0_EL0)
- .Case("pmevcntr1_el0", ARM64SYS::PMEVCNTR1_EL0)
- .Case("pmevcntr2_el0", ARM64SYS::PMEVCNTR2_EL0)
- .Case("pmevcntr3_el0", ARM64SYS::PMEVCNTR3_EL0)
- .Case("pmevcntr4_el0", ARM64SYS::PMEVCNTR4_EL0)
- .Case("pmevcntr5_el0", ARM64SYS::PMEVCNTR5_EL0)
- .Case("pmevcntr6_el0", ARM64SYS::PMEVCNTR6_EL0)
- .Case("pmevcntr7_el0", ARM64SYS::PMEVCNTR7_EL0)
- .Case("pmevcntr8_el0", ARM64SYS::PMEVCNTR8_EL0)
- .Case("pmevcntr9_el0", ARM64SYS::PMEVCNTR9_EL0)
- .Case("pmevcntr10_el0", ARM64SYS::PMEVCNTR10_EL0)
- .Case("pmevcntr11_el0", ARM64SYS::PMEVCNTR11_EL0)
- .Case("pmevcntr12_el0", ARM64SYS::PMEVCNTR12_EL0)
- .Case("pmevcntr13_el0", ARM64SYS::PMEVCNTR13_EL0)
- .Case("pmevcntr14_el0", ARM64SYS::PMEVCNTR14_EL0)
- .Case("pmevcntr15_el0", ARM64SYS::PMEVCNTR15_EL0)
- .Case("pmevcntr16_el0", ARM64SYS::PMEVCNTR16_EL0)
- .Case("pmevcntr17_el0", ARM64SYS::PMEVCNTR17_EL0)
- .Case("pmevcntr18_el0", ARM64SYS::PMEVCNTR18_EL0)
- .Case("pmevcntr19_el0", ARM64SYS::PMEVCNTR19_EL0)
- .Case("pmevcntr20_el0", ARM64SYS::PMEVCNTR20_EL0)
- .Case("pmevcntr21_el0", ARM64SYS::PMEVCNTR21_EL0)
- .Case("pmevcntr22_el0", ARM64SYS::PMEVCNTR22_EL0)
- .Case("pmevcntr23_el0", ARM64SYS::PMEVCNTR23_EL0)
- .Case("pmevcntr24_el0", ARM64SYS::PMEVCNTR24_EL0)
- .Case("pmevcntr25_el0", ARM64SYS::PMEVCNTR25_EL0)
- .Case("pmevcntr26_el0", ARM64SYS::PMEVCNTR26_EL0)
- .Case("pmevcntr27_el0", ARM64SYS::PMEVCNTR27_EL0)
- .Case("pmevcntr28_el0", ARM64SYS::PMEVCNTR28_EL0)
- .Case("pmevcntr29_el0", ARM64SYS::PMEVCNTR29_EL0)
- .Case("pmevcntr30_el0", ARM64SYS::PMEVCNTR30_EL0)
- .Case("pmevtyper0_el0", ARM64SYS::PMEVTYPER0_EL0)
- .Case("pmevtyper1_el0", ARM64SYS::PMEVTYPER1_EL0)
- .Case("pmevtyper2_el0", ARM64SYS::PMEVTYPER2_EL0)
- .Case("pmevtyper3_el0", ARM64SYS::PMEVTYPER3_EL0)
- .Case("pmevtyper4_el0", ARM64SYS::PMEVTYPER4_EL0)
- .Case("pmevtyper5_el0", ARM64SYS::PMEVTYPER5_EL0)
- .Case("pmevtyper6_el0", ARM64SYS::PMEVTYPER6_EL0)
- .Case("pmevtyper7_el0", ARM64SYS::PMEVTYPER7_EL0)
- .Case("pmevtyper8_el0", ARM64SYS::PMEVTYPER8_EL0)
- .Case("pmevtyper9_el0", ARM64SYS::PMEVTYPER9_EL0)
- .Case("pmevtyper10_el0", ARM64SYS::PMEVTYPER10_EL0)
- .Case("pmevtyper11_el0", ARM64SYS::PMEVTYPER11_EL0)
- .Case("pmevtyper12_el0", ARM64SYS::PMEVTYPER12_EL0)
- .Case("pmevtyper13_el0", ARM64SYS::PMEVTYPER13_EL0)
- .Case("pmevtyper14_el0", ARM64SYS::PMEVTYPER14_EL0)
- .Case("pmevtyper15_el0", ARM64SYS::PMEVTYPER15_EL0)
- .Case("pmevtyper16_el0", ARM64SYS::PMEVTYPER16_EL0)
- .Case("pmevtyper17_el0", ARM64SYS::PMEVTYPER17_EL0)
- .Case("pmevtyper18_el0", ARM64SYS::PMEVTYPER18_EL0)
- .Case("pmevtyper19_el0", ARM64SYS::PMEVTYPER19_EL0)
- .Case("pmevtyper20_el0", ARM64SYS::PMEVTYPER20_EL0)
- .Case("pmevtyper21_el0", ARM64SYS::PMEVTYPER21_EL0)
- .Case("pmevtyper22_el0", ARM64SYS::PMEVTYPER22_EL0)
- .Case("pmevtyper23_el0", ARM64SYS::PMEVTYPER23_EL0)
- .Case("pmevtyper24_el0", ARM64SYS::PMEVTYPER24_EL0)
- .Case("pmevtyper25_el0", ARM64SYS::PMEVTYPER25_EL0)
- .Case("pmevtyper26_el0", ARM64SYS::PMEVTYPER26_EL0)
- .Case("pmevtyper27_el0", ARM64SYS::PMEVTYPER27_EL0)
- .Case("pmevtyper28_el0", ARM64SYS::PMEVTYPER28_EL0)
- .Case("pmevtyper29_el0", ARM64SYS::PMEVTYPER29_EL0)
- .Case("pmevtyper30_el0", ARM64SYS::PMEVTYPER30_EL0)
- .Case("pmccfiltr_el0", ARM64SYS::PMCCFILTR_EL0)
- .Case("rmr_el3", ARM64SYS::RMR_EL3)
- .Case("rmr_el2", ARM64SYS::RMR_EL2)
- .Case("rmr_el1", ARM64SYS::RMR_EL1)
- .Case("cpm_ioacc_ctl_el3", ARM64SYS::CPM_IOACC_CTL_EL3)
- .Case("mdccsr_el0", ARM64SYS::MDCCSR_EL0)
- .Case("mdccint_el1", ARM64SYS::MDCCINT_EL1)
- .Case("dbgdtr_el0", ARM64SYS::DBGDTR_EL0)
- .Case("dbgdtrrx_el0", ARM64SYS::DBGDTRRX_EL0)
- .Case("dbgdtrtx_el0", ARM64SYS::DBGDTRTX_EL0)
- .Case("dbgvcr32_el2", ARM64SYS::DBGVCR32_EL2)
- .Case("osdtrrx_el1", ARM64SYS::OSDTRRX_EL1)
- .Case("mdscr_el1", ARM64SYS::MDSCR_EL1)
- .Case("osdtrtx_el1", ARM64SYS::OSDTRTX_EL1)
- .Case("oseccr_el11", ARM64SYS::OSECCR_EL11)
- .Case("dbgbvr0_el1", ARM64SYS::DBGBVR0_EL1)
- .Case("dbgbvr1_el1", ARM64SYS::DBGBVR1_EL1)
- .Case("dbgbvr2_el1", ARM64SYS::DBGBVR2_EL1)
- .Case("dbgbvr3_el1", ARM64SYS::DBGBVR3_EL1)
- .Case("dbgbvr4_el1", ARM64SYS::DBGBVR4_EL1)
- .Case("dbgbvr5_el1", ARM64SYS::DBGBVR5_EL1)
- .Case("dbgbvr6_el1", ARM64SYS::DBGBVR6_EL1)
- .Case("dbgbvr7_el1", ARM64SYS::DBGBVR7_EL1)
- .Case("dbgbvr8_el1", ARM64SYS::DBGBVR8_EL1)
- .Case("dbgbvr9_el1", ARM64SYS::DBGBVR9_EL1)
- .Case("dbgbvr10_el1", ARM64SYS::DBGBVR10_EL1)
- .Case("dbgbvr11_el1", ARM64SYS::DBGBVR11_EL1)
- .Case("dbgbvr12_el1", ARM64SYS::DBGBVR12_EL1)
- .Case("dbgbvr13_el1", ARM64SYS::DBGBVR13_EL1)
- .Case("dbgbvr14_el1", ARM64SYS::DBGBVR14_EL1)
- .Case("dbgbvr15_el1", ARM64SYS::DBGBVR15_EL1)
- .Case("dbgbcr0_el1", ARM64SYS::DBGBCR0_EL1)
- .Case("dbgbcr1_el1", ARM64SYS::DBGBCR1_EL1)
- .Case("dbgbcr2_el1", ARM64SYS::DBGBCR2_EL1)
- .Case("dbgbcr3_el1", ARM64SYS::DBGBCR3_EL1)
- .Case("dbgbcr4_el1", ARM64SYS::DBGBCR4_EL1)
- .Case("dbgbcr5_el1", ARM64SYS::DBGBCR5_EL1)
- .Case("dbgbcr6_el1", ARM64SYS::DBGBCR6_EL1)
- .Case("dbgbcr7_el1", ARM64SYS::DBGBCR7_EL1)
- .Case("dbgbcr8_el1", ARM64SYS::DBGBCR8_EL1)
- .Case("dbgbcr9_el1", ARM64SYS::DBGBCR9_EL1)
- .Case("dbgbcr10_el1", ARM64SYS::DBGBCR10_EL1)
- .Case("dbgbcr11_el1", ARM64SYS::DBGBCR11_EL1)
- .Case("dbgbcr12_el1", ARM64SYS::DBGBCR12_EL1)
- .Case("dbgbcr13_el1", ARM64SYS::DBGBCR13_EL1)
- .Case("dbgbcr14_el1", ARM64SYS::DBGBCR14_EL1)
- .Case("dbgbcr15_el1", ARM64SYS::DBGBCR15_EL1)
- .Case("dbgwvr0_el1", ARM64SYS::DBGWVR0_EL1)
- .Case("dbgwvr1_el1", ARM64SYS::DBGWVR1_EL1)
- .Case("dbgwvr2_el1", ARM64SYS::DBGWVR2_EL1)
- .Case("dbgwvr3_el1", ARM64SYS::DBGWVR3_EL1)
- .Case("dbgwvr4_el1", ARM64SYS::DBGWVR4_EL1)
- .Case("dbgwvr5_el1", ARM64SYS::DBGWVR5_EL1)
- .Case("dbgwvr6_el1", ARM64SYS::DBGWVR6_EL1)
- .Case("dbgwvr7_el1", ARM64SYS::DBGWVR7_EL1)
- .Case("dbgwvr8_el1", ARM64SYS::DBGWVR8_EL1)
- .Case("dbgwvr9_el1", ARM64SYS::DBGWVR9_EL1)
- .Case("dbgwvr10_el1", ARM64SYS::DBGWVR10_EL1)
- .Case("dbgwvr11_el1", ARM64SYS::DBGWVR11_EL1)
- .Case("dbgwvr12_el1", ARM64SYS::DBGWVR12_EL1)
- .Case("dbgwvr13_el1", ARM64SYS::DBGWVR13_EL1)
- .Case("dbgwvr14_el1", ARM64SYS::DBGWVR14_EL1)
- .Case("dbgwvr15_el1", ARM64SYS::DBGWVR15_EL1)
- .Case("dbgwcr0_el1", ARM64SYS::DBGWCR0_EL1)
- .Case("dbgwcr1_el1", ARM64SYS::DBGWCR1_EL1)
- .Case("dbgwcr2_el1", ARM64SYS::DBGWCR2_EL1)
- .Case("dbgwcr3_el1", ARM64SYS::DBGWCR3_EL1)
- .Case("dbgwcr4_el1", ARM64SYS::DBGWCR4_EL1)
- .Case("dbgwcr5_el1", ARM64SYS::DBGWCR5_EL1)
- .Case("dbgwcr6_el1", ARM64SYS::DBGWCR6_EL1)
- .Case("dbgwcr7_el1", ARM64SYS::DBGWCR7_EL1)
- .Case("dbgwcr8_el1", ARM64SYS::DBGWCR8_EL1)
- .Case("dbgwcr9_el1", ARM64SYS::DBGWCR9_EL1)
- .Case("dbgwcr10_el1", ARM64SYS::DBGWCR10_EL1)
- .Case("dbgwcr11_el1", ARM64SYS::DBGWCR11_EL1)
- .Case("dbgwcr12_el1", ARM64SYS::DBGWCR12_EL1)
- .Case("dbgwcr13_el1", ARM64SYS::DBGWCR13_EL1)
- .Case("dbgwcr14_el1", ARM64SYS::DBGWCR14_EL1)
- .Case("dbgwcr15_el1", ARM64SYS::DBGWCR15_EL1)
- .Case("mdrar_el1", ARM64SYS::MDRAR_EL1)
- .Case("oslar_el1", ARM64SYS::OSLAR_EL1)
- .Case("oslsr_el1", ARM64SYS::OSLSR_EL1)
- .Case("osdlr_el1", ARM64SYS::OSDLR_EL1)
- .Case("dbgprcr_el1", ARM64SYS::DBGPRCR_EL1)
- .Case("dbgclaimset_el1", ARM64SYS::DBGCLAIMSET_EL1)
- .Case("dbgclaimclr_el1", ARM64SYS::DBGCLAIMCLR_EL1)
- .Case("dbgauthstatus_el1", ARM64SYS::DBGAUTHSTATUS_EL1)
- .Case("dbgdevid2", ARM64SYS::DBGDEVID2)
- .Case("dbgdevid1", ARM64SYS::DBGDEVID1)
- .Case("dbgdevid0", ARM64SYS::DBGDEVID0)
- .Case("id_pfr0_el1", ARM64SYS::ID_PFR0_EL1)
- .Case("id_pfr1_el1", ARM64SYS::ID_PFR1_EL1)
- .Case("id_dfr0_el1", ARM64SYS::ID_DFR0_EL1)
- .Case("id_afr0_el1", ARM64SYS::ID_AFR0_EL1)
- .Case("id_isar0_el1", ARM64SYS::ID_ISAR0_EL1)
- .Case("id_isar1_el1", ARM64SYS::ID_ISAR1_EL1)
- .Case("id_isar2_el1", ARM64SYS::ID_ISAR2_EL1)
- .Case("id_isar3_el1", ARM64SYS::ID_ISAR3_EL1)
- .Case("id_isar4_el1", ARM64SYS::ID_ISAR4_EL1)
- .Case("id_isar5_el1", ARM64SYS::ID_ISAR5_EL1)
- .Case("afsr1_el1", ARM64SYS::AFSR1_EL1)
- .Case("afsr0_el1", ARM64SYS::AFSR0_EL1)
- .Case("revidr_el1", ARM64SYS::REVIDR_EL1)
- .Default(ARM64SYS::InvalidSystemReg);
- if (Reg != ARM64SYS::InvalidSystemReg) {
- // We matched a reg name, so create the operand.
- Operands.push_back(
- ARM64Operand::CreateSystemRegister(Reg, getLoc(), getContext()));
- Parser.Lex(); // Consume the register name.
- return MatchOperand_Success;
- }
-
- // Or we may have an identifier that encodes the sub-operands.
- // For example, s3_2_c15_c0_0.
- unsigned op0, op1, CRn, CRm, op2;
- std::string Desc = ID;
- if (std::sscanf(Desc.c_str(), "s%u_%u_c%u_c%u_%u", &op0, &op1, &CRn, &CRm,
- &op2) != 5)
- return MatchOperand_NoMatch;
- if ((op0 != 2 && op0 != 3) || op1 > 7 || CRn > 15 || CRm > 15 || op2 > 7)
- return MatchOperand_NoMatch;
-
- unsigned Val = op0 << 14 | op1 << 11 | CRn << 7 | CRm << 3 | op2;
- Operands.push_back(
- ARM64Operand::CreateSystemRegister(Val, getLoc(), getContext()));
- Parser.Lex(); // Consume the register name.
-
- return MatchOperand_Success;
-}
-
-ARM64AsmParser::OperandMatchResultTy
-ARM64AsmParser::tryParseCPSRField(OperandVector &Operands) {
+ARM64AsmParser::tryParseSysReg(OperandVector &Operands) {
const AsmToken &Tok = Parser.getTok();
if (Tok.isNot(AsmToken::Identifier))
return MatchOperand_NoMatch;
- ARM64SYS::CPSRField Field =
- StringSwitch<ARM64SYS::CPSRField>(Tok.getString().lower())
- .Case("spsel", ARM64SYS::cpsr_SPSel)
- .Case("daifset", ARM64SYS::cpsr_DAIFSet)
- .Case("daifclr", ARM64SYS::cpsr_DAIFClr)
- .Default(ARM64SYS::InvalidCPSRField);
- if (Field == ARM64SYS::InvalidCPSRField)
- return MatchOperand_NoMatch;
- Operands.push_back(
- ARM64Operand::CreateCPSRField(Field, getLoc(), getContext()));
- Parser.Lex(); // Consume the register name.
+ Operands.push_back(ARM64Operand::CreateSysReg(Tok.getString(), getLoc(),
+ getContext()));
+ Parser.Lex(); // Eat identifier
return MatchOperand_Success;
}
@@ -3004,7 +2660,7 @@ bool ARM64AsmParser::tryParseVectorRegister(OperandVector &Operands) {
SMLoc S = getLoc();
// Check for a vector register specifier first.
StringRef Kind;
- int64_t Reg = tryMatchVectorRegister(Kind);
+ int64_t Reg = tryMatchVectorRegister(Kind, false);
if (Reg == -1)
return true;
Operands.push_back(
@@ -3354,36 +3010,57 @@ bool ARM64AsmParser::parseVectorList(OperandVector &Operands) {
SMLoc S = getLoc();
Parser.Lex(); // Eat left bracket token.
StringRef Kind;
- int64_t FirstReg = tryMatchVectorRegister(Kind);
+ int64_t FirstReg = tryMatchVectorRegister(Kind, true);
if (FirstReg == -1)
- return Error(getLoc(), "vector register expected");
+ return true;
int64_t PrevReg = FirstReg;
unsigned Count = 1;
- while (Parser.getTok().isNot(AsmToken::RCurly)) {
- if (Parser.getTok().is(AsmToken::EndOfStatement))
- Error(getLoc(), "'}' expected");
- if (Parser.getTok().isNot(AsmToken::Comma))
- return Error(getLoc(), "',' expected");
- Parser.Lex(); // Eat the comma token.
+ if (Parser.getTok().is(AsmToken::Minus)) {
+ Parser.Lex(); // Eat the minus.
SMLoc Loc = getLoc();
StringRef NextKind;
- int64_t Reg = tryMatchVectorRegister(NextKind);
+ int64_t Reg = tryMatchVectorRegister(NextKind, true);
if (Reg == -1)
- return Error(Loc, "vector register expected");
+ return true;
// Any Kind suffices must match on all regs in the list.
if (Kind != NextKind)
return Error(Loc, "mismatched register size suffix");
- // Registers must be incremental (with wraparound at 31)
- if (getContext().getRegisterInfo()->getEncodingValue(Reg) !=
- (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32)
- return Error(Loc, "registers must be sequential");
+ unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg);
- PrevReg = Reg;
- ++Count;
+ if (Space == 0 || Space > 3) {
+ return Error(Loc, "invalid number of vectors");
+ }
+
+ Count += Space;
}
+ else {
+ while (Parser.getTok().is(AsmToken::Comma)) {
+ Parser.Lex(); // Eat the comma token.
+
+ SMLoc Loc = getLoc();
+ StringRef NextKind;
+ int64_t Reg = tryMatchVectorRegister(NextKind, true);
+ if (Reg == -1)
+ return true;
+ // Any Kind suffices must match on all regs in the list.
+ if (Kind != NextKind)
+ return Error(Loc, "mismatched register size suffix");
+
+ // Registers must be incremental (with wraparound at 31)
+ if (getContext().getRegisterInfo()->getEncodingValue(Reg) !=
+ (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32)
+ return Error(Loc, "registers must be sequential");
+
+ PrevReg = Reg;
+ ++Count;
+ }
+ }
+
+ if (Parser.getTok().is(AsmToken::EndOfStatement))
+ Error(getLoc(), "'}' expected");
Parser.Lex(); // Eat the '}' token.
unsigned NumElements = 0;
@@ -3542,7 +3219,7 @@ bool ARM64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
SMLoc SuffixLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
(Head.data() - Name.data()));
unsigned CC = parseCondCodeString(Head);
- if (CC == ~0U)
+ if (CC == ARM64CC::Invalid)
return Error(SuffixLoc, "invalid condition code");
const MCExpr *CCExpr = MCConstantExpr::Create(CC, getContext());
Operands.push_back(
@@ -3642,7 +3319,7 @@ static bool isGPR32Register(unsigned Reg) {
case W7: case W8: case W9: case W10: case W11: case W12: case W13:
case W14: case W15: case W16: case W17: case W18: case W19: case W20:
case W21: case W22: case W23: case W24: case W25: case W26: case W27:
- case W28: case W29: case W30: case WSP:
+ case W28: case W29: case W30: case WSP: case WZR:
return true;
}
return false;
@@ -4055,9 +3732,9 @@ bool ARM64AsmParser::validateInstruction(MCInst &Inst,
}
}
-static void rewriteMOV(ARM64AsmParser::OperandVector &Operands,
- StringRef mnemonic, uint64_t imm, unsigned shift,
- MCContext &Context) {
+static void rewriteMOVI(ARM64AsmParser::OperandVector &Operands,
+ StringRef mnemonic, uint64_t imm, unsigned shift,
+ MCContext &Context) {
ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[0]);
ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
Operands[0] =
@@ -4073,6 +3750,43 @@ static void rewriteMOV(ARM64AsmParser::OperandVector &Operands,
delete Op;
}
+static void rewriteMOVRSP(ARM64AsmParser::OperandVector &Operands,
+ MCContext &Context) {
+ ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[0]);
+ ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
+ Operands[0] =
+ ARM64Operand::CreateToken("add", false, Op->getStartLoc(), Context);
+
+ const MCExpr *Imm = MCConstantExpr::Create(0, Context);
+ Operands.push_back(ARM64Operand::CreateImm(Imm, Op2->getStartLoc(),
+ Op2->getEndLoc(), Context));
+ Operands.push_back(ARM64Operand::CreateShifter(
+ ARM64_AM::LSL, 0, Op2->getStartLoc(), Op2->getEndLoc(), Context));
+
+ delete Op;
+}
+
+static void rewriteMOVR(ARM64AsmParser::OperandVector &Operands,
+ MCContext &Context) {
+ ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[0]);
+ ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
+ Operands[0] =
+ ARM64Operand::CreateToken("orr", false, Op->getStartLoc(), Context);
+
+ // Operands[2] becomes Operands[3].
+ Operands.push_back(Operands[2]);
+ // And Operands[2] becomes ZR.
+ unsigned ZeroReg = ARM64::XZR;
+ if (isGPR32Register(Operands[2]->getReg()))
+ ZeroReg = ARM64::WZR;
+
+ Operands[2] =
+ ARM64Operand::CreateReg(ZeroReg, false, Op2->getStartLoc(),
+ Op2->getEndLoc(), Context);
+
+ delete Op;
+}
+
bool ARM64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode) {
switch (ErrCode) {
case Match_MissingFeature:
@@ -4108,6 +3822,8 @@ bool ARM64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode) {
return Error(Loc, "immediate must be an integer in range [1,32].");
case Match_InvalidImm1_64:
return Error(Loc, "immediate must be an integer in range [1,64].");
+ case Match_InvalidLabel:
+ return Error(Loc, "expected label or encodable integer pc offset");
case Match_MnemonicFail:
return Error(Loc, "unrecognized instruction mnemonic");
default:
@@ -4141,8 +3857,7 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
// Insert WZR or XZR as destination operand.
ARM64Operand *RegOp = static_cast<ARM64Operand *>(Operands[1]);
unsigned ZeroReg;
- if (RegOp->isReg() &&
- (isGPR32Register(RegOp->getReg()) || RegOp->getReg() == ARM64::WZR))
+ if (RegOp->isReg() && isGPR32Register(RegOp->getReg()))
ZeroReg = ARM64::WZR;
else
ZeroReg = ARM64::XZR;
@@ -4162,6 +3877,7 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
// FIXME: Catching this here is a total hack, and we should use tblgen
// support to implement this instead as soon as it is available.
+ ARM64Operand *Op1 = static_cast<ARM64Operand *>(Operands[1]);
ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
if (Op2->isImm()) {
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op2->getImm())) {
@@ -4178,36 +3894,47 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
// MOVK Rd, imm << 0
if ((Val & 0xFFFF) == Val)
- rewriteMOV(Operands, "movz", Val, 0, getContext());
+ rewriteMOVI(Operands, "movz", Val, 0, getContext());
// MOVK Rd, imm << 16
else if ((Val & 0xFFFF0000ULL) == Val)
- rewriteMOV(Operands, "movz", Val, 16, getContext());
+ rewriteMOVI(Operands, "movz", Val, 16, getContext());
// MOVK Rd, imm << 32
else if ((Val & 0xFFFF00000000ULL) == Val)
- rewriteMOV(Operands, "movz", Val, 32, getContext());
+ rewriteMOVI(Operands, "movz", Val, 32, getContext());
// MOVK Rd, imm << 48
else if ((Val & 0xFFFF000000000000ULL) == Val)
- rewriteMOV(Operands, "movz", Val, 48, getContext());
+ rewriteMOVI(Operands, "movz", Val, 48, getContext());
// MOVN Rd, (~imm << 0)
else if ((NVal & 0xFFFFULL) == NVal)
- rewriteMOV(Operands, "movn", NVal, 0, getContext());
+ rewriteMOVI(Operands, "movn", NVal, 0, getContext());
// MOVN Rd, ~(imm << 16)
else if ((NVal & 0xFFFF0000ULL) == NVal)
- rewriteMOV(Operands, "movn", NVal, 16, getContext());
+ rewriteMOVI(Operands, "movn", NVal, 16, getContext());
// MOVN Rd, ~(imm << 32)
else if ((NVal & 0xFFFF00000000ULL) == NVal)
- rewriteMOV(Operands, "movn", NVal, 32, getContext());
+ rewriteMOVI(Operands, "movn", NVal, 32, getContext());
// MOVN Rd, ~(imm << 48)
else if ((NVal & 0xFFFF000000000000ULL) == NVal)
- rewriteMOV(Operands, "movn", NVal, 48, getContext());
+ rewriteMOVI(Operands, "movn", NVal, 48, getContext());
}
+ } else if (Op1->isReg() && Op2->isReg()) {
+ // reg->reg move.
+ unsigned Reg1 = Op1->getReg();
+ unsigned Reg2 = Op2->getReg();
+ if ((Reg1 == ARM64::SP && isGPR64Reg(Reg2)) ||
+ (Reg2 == ARM64::SP && isGPR64Reg(Reg1)) ||
+ (Reg1 == ARM64::WSP && isGPR32Register(Reg2)) ||
+ (Reg2 == ARM64::WSP && isGPR32Register(Reg1)))
+ rewriteMOVRSP(Operands, getContext());
+ else
+ rewriteMOVR(Operands, getContext());
}
} else if (NumOperands == 4) {
if (Tok == "add" || Tok == "adds" || Tok == "sub" || Tok == "subs") {
@@ -4251,7 +3978,7 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
uint64_t Op3Val = Op3CE->getValue();
uint64_t NewOp3Val = 0;
uint64_t NewOp4Val = 0;
- if (isGPR32Register(Op2->getReg()) || Op2->getReg() == ARM64::WZR) {
+ if (isGPR32Register(Op2->getReg())) {
NewOp3Val = (32 - Op3Val) & 0x1f;
NewOp4Val = 31 - Op3Val;
} else {
@@ -4584,7 +4311,8 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidImm1_8:
case Match_InvalidImm1_16:
case Match_InvalidImm1_32:
- case Match_InvalidImm1_64: {
+ case Match_InvalidImm1_64:
+ case Match_InvalidLabel: {
// Any time we get here, there's nothing fancy to do. Just get the
// operand SMLoc and display the diagnostic.
SMLoc ErrorLoc = ((ARM64Operand *)Operands[ErrorInfo])->getStartLoc();
diff --git a/lib/Target/ARM64/CMakeLists.txt b/lib/Target/ARM64/CMakeLists.txt
index 6de861c..56ba3b7 100644
--- a/lib/Target/ARM64/CMakeLists.txt
+++ b/lib/Target/ARM64/CMakeLists.txt
@@ -48,3 +48,4 @@ add_subdirectory(AsmParser)
add_subdirectory(Disassembler)
add_subdirectory(InstPrinter)
add_subdirectory(MCTargetDesc)
+add_subdirectory(Utils)
diff --git a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
index 44c501f..8f9b79c 100644
--- a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
+++ b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
@@ -14,8 +14,8 @@
#include "ARM64Disassembler.h"
#include "ARM64Subtarget.h"
-#include "MCTargetDesc/ARM64BaseInfo.h"
#include "MCTargetDesc/ARM64AddressingModes.h"
+#include "Utils/ARM64BaseInfo.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCContext.h"
@@ -82,14 +82,19 @@ static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
-static DecodeStatus DecodeFixedPointScaleImm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address,
- const void *Decoder);
+static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
+ uint64_t Address,
+ const void *Decoder);
+static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
+ uint64_t Address,
+ const void *Decoder);
static DecodeStatus DecodeCondBranchTarget(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder);
-static DecodeStatus DecodeSystemRegister(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
uint32_t insn,
uint64_t Address,
@@ -742,9 +747,18 @@ static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
return Success;
}
-static DecodeStatus DecodeFixedPointScaleImm(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Addr,
- const void *Decoder) {
+static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
+ uint64_t Addr,
+ const void *Decoder) {
+ // scale{5} is asserted as 1 in tblgen.
+ Imm |= 0x20;
+ Inst.addOperand(MCOperand::CreateImm(64 - Imm));
+ return Success;
+}
+
+static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
+ uint64_t Addr,
+ const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(64 - Imm));
return Success;
}
@@ -765,11 +779,28 @@ static DecodeStatus DecodeCondBranchTarget(llvm::MCInst &Inst, unsigned Imm,
return Success;
}
-static DecodeStatus DecodeSystemRegister(llvm::MCInst &Inst, unsigned Imm,
- uint64_t Address,
- const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(Imm | 0x8000));
- return Success;
+static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
+ uint64_t Address,
+ const void *Decoder) {
+ Imm |= 0x8000;
+ Inst.addOperand(MCOperand::CreateImm(Imm));
+
+ bool ValidNamed;
+ (void)ARM64SysReg::MRSMapper().toString(Imm, ValidNamed);
+
+ return ValidNamed ? Success : Fail;
+}
+
+static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
+ uint64_t Address,
+ const void *Decoder) {
+ Imm |= 0x8000;
+ Inst.addOperand(MCOperand::CreateImm(Imm));
+
+ bool ValidNamed;
+ (void)ARM64SysReg::MSRMapper().toString(Imm, ValidNamed);
+
+ return ValidNamed ? Success : Fail;
}
static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
@@ -854,6 +885,14 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
switch (Inst.getOpcode()) {
default:
return Fail;
+ case ARM64::ADDWrs:
+ case ARM64::ADDSWrs:
+ case ARM64::SUBWrs:
+ case ARM64::SUBSWrs:
+ // if shift == '11' then ReservedValue()
+ if (shiftHi == 0x3)
+ return Fail;
+ // Deliberate fallthrough
case ARM64::ANDWrs:
case ARM64::ANDSWrs:
case ARM64::BICWrs:
@@ -861,16 +900,23 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
case ARM64::ORRWrs:
case ARM64::ORNWrs:
case ARM64::EORWrs:
- case ARM64::EONWrs:
- case ARM64::ADDWrs:
- case ARM64::ADDSWrs:
- case ARM64::SUBWrs:
- case ARM64::SUBSWrs: {
+ case ARM64::EONWrs: {
+ // if sf == '0' and imm6<5> == '1' then ReservedValue()
+ if (shiftLo >> 5 == 1)
+ return Fail;
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break;
}
+ case ARM64::ADDXrs:
+ case ARM64::ADDSXrs:
+ case ARM64::SUBXrs:
+ case ARM64::SUBSXrs:
+ // if shift == '11' then ReservedValue()
+ if (shiftHi == 0x3)
+ return Fail;
+ // Deliberate fallthrough
case ARM64::ANDXrs:
case ARM64::ANDSXrs:
case ARM64::BICXrs:
@@ -879,10 +925,6 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
case ARM64::ORNXrs:
case ARM64::EORXrs:
case ARM64::EONXrs:
- case ARM64::ADDXrs:
- case ARM64::ADDSXrs:
- case ARM64::SUBXrs:
- case ARM64::SUBSXrs:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
@@ -906,6 +948,8 @@ static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
case ARM64::MOVZWi:
case ARM64::MOVNWi:
case ARM64::MOVKWi:
+ if (shift & (1U << 5))
+ return Fail;
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
break;
case ARM64::MOVZXi:
@@ -1262,79 +1306,72 @@ static DecodeStatus DecodeRegOffsetLdStInstruction(llvm::MCInst &Inst,
unsigned Rm = fieldFromInstruction(insn, 16, 5);
unsigned extendHi = fieldFromInstruction(insn, 13, 3);
unsigned extendLo = fieldFromInstruction(insn, 12, 1);
- unsigned extend = 0;
+ unsigned extend = (extendHi << 1) | extendLo;
+
+ // All RO load-store instructions are undefined if option == 00x or 10x.
+ if (extend >> 2 == 0x0 || extend >> 2 == 0x2)
+ return Fail;
switch (Inst.getOpcode()) {
default:
return Fail;
case ARM64::LDRSWro:
- extend = (extendHi << 1) | extendLo;
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRXro:
case ARM64::STRXro:
- extend = (extendHi << 1) | extendLo;
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRWro:
case ARM64::STRWro:
- extend = (extendHi << 1) | extendLo;
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRQro:
case ARM64::STRQro:
- extend = (extendHi << 1) | extendLo;
DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRDro:
case ARM64::STRDro:
- extend = (extendHi << 1) | extendLo;
DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRSro:
case ARM64::STRSro:
- extend = (extendHi << 1) | extendLo;
DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRHro:
- extend = (extendHi << 1) | extendLo;
+ case ARM64::STRHro:
DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRBro:
- extend = (extendHi << 1) | extendLo;
+ case ARM64::STRBro:
DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRBBro:
case ARM64::STRBBro:
case ARM64::LDRSBWro:
- extend = (extendHi << 1) | extendLo;
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRHHro:
case ARM64::STRHHro:
case ARM64::LDRSHWro:
- extend = (extendHi << 1) | extendLo;
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRSHXro:
- extend = (extendHi << 1) | extendLo;
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::LDRSBXro:
- extend = (extendHi << 1) | extendLo;
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case ARM64::PRFMro:
- extend = (extendHi << 1) | extendLo;
Inst.addOperand(MCOperand::CreateImm(Rt));
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- if (extendHi == 0x3)
+ if ((extendHi & 0x3) == 0x3)
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
else
- DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
+ DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
Inst.addOperand(MCOperand::CreateImm(extend));
return Success;
@@ -1348,6 +1385,10 @@ static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
unsigned Rm = fieldFromInstruction(insn, 16, 5);
unsigned extend = fieldFromInstruction(insn, 10, 6);
+ unsigned shift = extend & 0x7;
+ if (shift > 4)
+ return Fail;
+
switch (Inst.getOpcode()) {
default:
return Fail;
@@ -1376,13 +1417,17 @@ static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break;
case ARM64::ADDXrx64:
- case ARM64::ADDSXrx64:
case ARM64::SUBXrx64:
- case ARM64::SUBSXrx64:
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
break;
+ case ARM64::SUBSXrx64:
+ case ARM64::ADDSXrx64:
+ DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+ DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
+ break;
}
Inst.addOperand(MCOperand::CreateImm(extend));
@@ -1398,13 +1443,19 @@ static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
unsigned imm;
if (Datasize) {
- DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
+ if (Inst.getOpcode() == ARM64::ANDSXri)
+ DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+ else
+ DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
imm = fieldFromInstruction(insn, 10, 13);
if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 64))
return Fail;
} else {
- DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
+ if (Inst.getOpcode() == ARM64::ANDSWri)
+ DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
+ else
+ DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
imm = fieldFromInstruction(insn, 10, 12);
if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 32))
@@ -1550,10 +1601,15 @@ static DecodeStatus DecodeSystemCPSRInstruction(llvm::MCInst &Inst,
uint64_t op2 = fieldFromInstruction(insn, 5, 3);
uint64_t crm = fieldFromInstruction(insn, 8, 4);
- Inst.addOperand(MCOperand::CreateImm((op1 << 3) | op2));
+ uint64_t cpsr_field = (op1 << 3) | op2;
+
+ Inst.addOperand(MCOperand::CreateImm(cpsr_field));
Inst.addOperand(MCOperand::CreateImm(crm));
- return Success;
+ bool ValidNamed;
+ (void)ARM64PState::PStateMapper().toString(cpsr_field, ValidNamed);
+
+ return ValidNamed ? Success : Fail;
}
static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
@@ -1955,7 +2011,7 @@ static DecodeStatus DecodeSIMDLdStSingle(llvm::MCInst &Inst, uint32_t insn,
Inst.addOperand(MCOperand::CreateImm(index));
}
- DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
switch (Inst.getOpcode()) {
case ARM64::ST1i8_POST:
@@ -2116,7 +2172,7 @@ static DecodeStatus DecodeSIMDLdStSingleTied(llvm::MCInst &Inst, uint32_t insn,
}
Inst.addOperand(MCOperand::CreateImm(index));
- DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
switch (Inst.getOpcode()) {
case ARM64::LD1i8_POST:
diff --git a/lib/Target/ARM64/Disassembler/LLVMBuild.txt b/lib/Target/ARM64/Disassembler/LLVMBuild.txt
index 5935ee6..293e1be 100644
--- a/lib/Target/ARM64/Disassembler/LLVMBuild.txt
+++ b/lib/Target/ARM64/Disassembler/LLVMBuild.txt
@@ -19,6 +19,6 @@
type = Library
name = ARM64Disassembler
parent = ARM64
-required_libraries = ARM64Desc ARM64Info MC Support
+required_libraries = ARM64Desc ARM64Info ARM64Utils MC Support
add_to_library_groups = ARM64
diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
index bb90707..efe5e15 100644
--- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
+++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
@@ -14,7 +14,7 @@
#define DEBUG_TYPE "asm-printer"
#include "ARM64InstPrinter.h"
#include "MCTargetDesc/ARM64AddressingModes.h"
-#include "MCTargetDesc/ARM64BaseInfo.h"
+#include "Utils/ARM64BaseInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/MC/MCInst.h"
@@ -52,11 +52,11 @@ void ARM64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot) {
- // Check for special encodings and print the cannonical alias instead.
+ // Check for special encodings and print the canonical alias instead.
unsigned Opcode = MI->getOpcode();
- if (Opcode == ARM64::SYS || Opcode == ARM64::SYSxt)
+ if (Opcode == ARM64::SYSxt)
if (printSysAlias(MI, O)) {
printAnnotation(O, Annot);
return;
@@ -82,29 +82,29 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
const MCOperand &Op2 = MI->getOperand(2);
const MCOperand &Op3 = MI->getOperand(3);
- if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
- bool IsSigned = (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri);
- const char *AsmMnemonic = 0;
+ // *xt{b,h} is only valid for 32-bit operations.
+ if (Opcode == ARM64::SBFMWri || Opcode == ARM64::UBFMWri) {
+ if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
+ bool IsSigned = Opcode == ARM64::SBFMWri;
+ const char *AsmMnemonic = 0;
- switch (Op3.getImm()) {
- default:
- break;
- case 7:
- AsmMnemonic = IsSigned ? "sxtb" : "uxtb";
- break;
- case 15:
- AsmMnemonic = IsSigned ? "sxth" : "uxth";
- break;
- case 31:
- AsmMnemonic = IsSigned ? "sxtw" : "uxtw";
- break;
- }
+ switch (Op3.getImm()) {
+ default:
+ break;
+ case 7:
+ AsmMnemonic = IsSigned ? "sxtb" : "uxtb";
+ break;
+ case 15:
+ AsmMnemonic = IsSigned ? "sxth" : "uxth";
+ break;
+ }
- if (AsmMnemonic) {
- O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
- << ", " << getRegisterName(Op1.getReg());
- printAnnotation(O, Annot);
- return;
+ if (AsmMnemonic) {
+ O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
+ << ", " << getRegisterName(Op1.getReg());
+ printAnnotation(O, Annot);
+ return;
+ }
}
}
@@ -189,6 +189,14 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
return;
}
+ // ORN Wn, WZR, Wm{, lshift #imm} ==> MVN Wn, Wm{, lshift #imm}
+ // ORN Xn, XZR, Xm{, lshift #imm} ==> MVN Xn, Xm{, lshift #imm}
+ if ((Opcode == ARM64::ORNWrs && MI->getOperand(1).getReg() == ARM64::WZR) ||
+ (Opcode == ARM64::ORNXrs && MI->getOperand(1).getReg() == ARM64::XZR)) {
+ O << "\tmvn\t" << getRegisterName(MI->getOperand(0).getReg()) << ", ";
+ printShiftedRegister(MI, 2, O);
+ return;
+ }
// SUBS WZR, Wn, #imm ==> CMP Wn, #imm
// SUBS XZR, Xn, #imm ==> CMP Xn, #imm
if ((Opcode == ARM64::SUBSWri && MI->getOperand(0).getReg() == ARM64::WZR) ||
@@ -250,6 +258,38 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
printExtend(MI, 3, O);
return;
}
+ // ADD WSP, Wn, #0 ==> MOV WSP, Wn
+ if (Opcode == ARM64::ADDWri && (MI->getOperand(0).getReg() == ARM64::WSP ||
+ MI->getOperand(1).getReg() == ARM64::WSP) &&
+ MI->getOperand(2).getImm() == 0 &&
+ ARM64_AM::getShiftValue(MI->getOperand(3).getImm()) == 0) {
+ O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
+ << ", " << getRegisterName(MI->getOperand(1).getReg());
+ return;
+ }
+ // ADD XSP, Wn, #0 ==> MOV XSP, Wn
+ if (Opcode == ARM64::ADDXri && (MI->getOperand(0).getReg() == ARM64::SP ||
+ MI->getOperand(1).getReg() == ARM64::SP) &&
+ MI->getOperand(2).getImm() == 0 &&
+ ARM64_AM::getShiftValue(MI->getOperand(3).getImm()) == 0) {
+ O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
+ << ", " << getRegisterName(MI->getOperand(1).getReg());
+ return;
+ }
+ // ORR Wn, WZR, Wm ==> MOV Wn, Wm
+ if (Opcode == ARM64::ORRWrs && MI->getOperand(1).getReg() == ARM64::WZR &&
+ MI->getOperand(3).getImm() == 0) {
+ O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
+ << ", " << getRegisterName(MI->getOperand(2).getReg());
+ return;
+ }
+ // ORR Xn, XZR, Xm ==> MOV Xn, Xm
+ if (Opcode == ARM64::ORRXrs && MI->getOperand(1).getReg() == ARM64::XZR &&
+ MI->getOperand(3).getImm() == 0) {
+ O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
+ << ", " << getRegisterName(MI->getOperand(2).getReg());
+ return;
+ }
if (!printAliasInstr(MI, O))
printInstruction(MI, O);
@@ -708,8 +748,7 @@ void ARM64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
bool ARM64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
#ifndef NDEBUG
unsigned Opcode = MI->getOpcode();
- assert((Opcode == ARM64::SYS || Opcode == ARM64::SYSxt) &&
- "Invalid opcode for SYS alias!");
+ assert(Opcode == ARM64::SYSxt && "Invalid opcode for SYS alias!");
#endif
const char *Asm = 0;
@@ -849,6 +888,20 @@ bool ARM64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
break;
}
break;
+ case 0:
+ switch (Op1Val) {
+ default:
+ break;
+ case 4:
+ switch (Op2Val) {
+ default:
+ break;
+ case 1: Asm = "tlbi\tipas2e1is"; break;
+ case 5: Asm = "tlbi\tipas2le1is"; break;
+ }
+ break;
+ }
+ break;
case 4:
switch (Op1Val) {
default:
@@ -905,9 +958,11 @@ bool ARM64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
}
if (Asm) {
+ unsigned Reg = MI->getOperand(4).getReg();
+
O << '\t' << Asm;
- if (MI->getNumOperands() == 5)
- O << ", " << getRegisterName(MI->getOperand(4).getReg());
+ if (StringRef(Asm).lower().find("all") == StringRef::npos)
+ O << ", " << getRegisterName(Reg);
}
return Asm != 0;
@@ -1083,8 +1138,10 @@ void ARM64InstPrinter::printExtend(const MCInst *MI, unsigned OpNum,
if (ExtType == ARM64_AM::UXTW || ExtType == ARM64_AM::UXTX) {
unsigned Dest = MI->getOperand(0).getReg();
unsigned Src1 = MI->getOperand(1).getReg();
- if (Dest == ARM64::SP || Dest == ARM64::WSP || Src1 == ARM64::SP ||
- Src1 == ARM64::WSP) {
+ if ( ((Dest == ARM64::SP || Src1 == ARM64::SP) &&
+ ExtType == ARM64_AM::UXTX) ||
+ ((Dest == ARM64::WSP || Src1 == ARM64::WSP) &&
+ ExtType == ARM64_AM::UXTW) ) {
if (ShiftVal != 0)
O << ", lsl #" << ShiftVal;
return;
@@ -1098,8 +1155,7 @@ void ARM64InstPrinter::printExtend(const MCInst *MI, unsigned OpNum,
void ARM64InstPrinter::printDotCondCode(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
- if (CC != ARM64CC::AL)
- O << '.' << ARM64CC::getCondCodeName(CC);
+ O << '.' << ARM64CC::getCondCodeName(CC);
}
void ARM64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
@@ -1142,11 +1198,26 @@ void ARM64InstPrinter::printAMIndexed(const MCInst *MI, unsigned OpNum,
O << ']';
}
+void ARM64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
+ unsigned Scale, raw_ostream &O) {
+ const MCOperand MO1 = MI->getOperand(OpNum + 1);
+ O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
+ if (MO1.isImm()) {
+ O << ", #" << (MO1.getImm() * Scale);
+ } else {
+ assert(MO1.isExpr() && "Unexpected operand type!");
+ O << ", " << *MO1.getExpr();
+ }
+ O << ']';
+}
+
void ARM64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
unsigned prfop = MI->getOperand(OpNum).getImm();
- if (ARM64_AM::isNamedPrefetchOp(prfop))
- O << ARM64_AM::getPrefetchOpName((ARM64_AM::PrefetchOp)prfop);
+ bool Valid;
+ StringRef Name = ARM64PRFM::PRFMMapper().toString(prfop, Valid);
+ if (Valid)
+ O << Name;
else
O << '#' << prfop;
}
@@ -1387,37 +1458,54 @@ void ARM64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
void ARM64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
unsigned Val = MI->getOperand(OpNo).getImm();
- const char *Name = ARM64SYS::getBarrierOptName((ARM64SYS::BarrierOption)Val);
- if (Name)
+ unsigned Opcode = MI->getOpcode();
+
+ bool Valid;
+ StringRef Name;
+ if (Opcode == ARM64::ISB)
+ Name = ARM64ISB::ISBMapper().toString(Val, Valid);
+ else
+ Name = ARM64DB::DBarrierMapper().toString(Val, Valid);
+ if (Valid)
O << Name;
else
O << "#" << Val;
}
-void ARM64InstPrinter::printSystemRegister(const MCInst *MI, unsigned OpNo,
+void ARM64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
unsigned Val = MI->getOperand(OpNo).getImm();
- const char *Name =
- ARM64SYS::getSystemRegisterName((ARM64SYS::SystemRegister)Val);
- if (Name) {
- O << Name;
- return;
- }
- unsigned Op0 = 2 | ((Val >> 14) & 1);
- unsigned Op1 = (Val >> 11) & 7;
- unsigned CRn = (Val >> 7) & 0xf;
- unsigned CRm = (Val >> 3) & 0xf;
- unsigned Op2 = Val & 7;
+ bool Valid;
+ auto Mapper = ARM64SysReg::MRSMapper();
+ StringRef Name = Mapper.toString(Val, Valid);
+
+ if (Valid)
+ O << StringRef(Name.str()).upper();
+}
+
+void ARM64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O) {
+ unsigned Val = MI->getOperand(OpNo).getImm();
- O << 'S' << Op0 << '_' << Op1 << "_C" << CRn << "_C" << CRm << '_' << Op2;
+ bool Valid;
+ auto Mapper = ARM64SysReg::MSRMapper();
+ StringRef Name = Mapper.toString(Val, Valid);
+
+ if (Valid)
+ O << StringRef(Name.str()).upper();
}
void ARM64InstPrinter::printSystemCPSRField(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
unsigned Val = MI->getOperand(OpNo).getImm();
- const char *Name = ARM64SYS::getCPSRFieldName((ARM64SYS::CPSRField)Val);
- O << Name;
+
+ bool Valid;
+ StringRef Name = ARM64PState::PStateMapper().toString(Val, Valid);
+ if (Valid)
+ O << StringRef(Name.str()).upper();
+ else
+ O << "#" << Val;
}
void ARM64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h
index ff66ff0..778e865 100644
--- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h
+++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h
@@ -73,28 +73,48 @@ protected:
raw_ostream &O);
void printAMIndexed(const MCInst *MI, unsigned OpNum, unsigned Scale,
raw_ostream &O);
+ void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
+ raw_ostream &O);
void printAMIndexed128(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 16, O);
}
+ void printAMIndexed128WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
+ printAMIndexedWB(MI, OpNum, 16, O);
+ }
void printAMIndexed64(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 8, O);
}
+ void printAMIndexed64WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
+ printAMIndexedWB(MI, OpNum, 8, O);
+ }
void printAMIndexed32(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 4, O);
}
+ void printAMIndexed32WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
+ printAMIndexedWB(MI, OpNum, 4, O);
+ }
void printAMIndexed16(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 2, O);
}
+ void printAMIndexed16WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
+ printAMIndexedWB(MI, OpNum, 2, O);
+ }
void printAMIndexed8(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 1, O);
}
+ void printAMIndexed8WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
+ printAMIndexedWB(MI, OpNum, 1, O);
+ }
void printAMUnscaled(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 1, O);
}
+ void printAMUnscaledWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
+ printAMIndexedWB(MI, OpNum, 1, O);
+ }
void printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printImmScale4(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printImmScale8(const MCInst *MI, unsigned OpNum, raw_ostream &O);
@@ -132,7 +152,8 @@ protected:
void printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAdrpLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printBarrierOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+ void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+ void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printSystemCPSRField(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
};
diff --git a/lib/Target/ARM64/InstPrinter/LLVMBuild.txt b/lib/Target/ARM64/InstPrinter/LLVMBuild.txt
index 2ec83d2..7ab4392 100644
--- a/lib/Target/ARM64/InstPrinter/LLVMBuild.txt
+++ b/lib/Target/ARM64/InstPrinter/LLVMBuild.txt
@@ -19,6 +19,6 @@
type = Library
name = ARM64AsmPrinter
parent = ARM64
-required_libraries = MC Support
+required_libraries = ARM64Utils MC Support
add_to_library_groups = ARM64
diff --git a/lib/Target/ARM64/LLVMBuild.txt b/lib/Target/ARM64/LLVMBuild.txt
index 45b0628..0f4f865 100644
--- a/lib/Target/ARM64/LLVMBuild.txt
+++ b/lib/Target/ARM64/LLVMBuild.txt
@@ -16,7 +16,7 @@
;===------------------------------------------------------------------------===;
[common]
-subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo
+subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils
[component_0]
type = TargetGroup
@@ -31,6 +31,6 @@ has_jit = 1
type = Library
name = ARM64CodeGen
parent = ARM64
-required_libraries = ARM64AsmPrinter ARM64Desc ARM64Info Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target
+required_libraries = ARM64AsmPrinter ARM64Desc ARM64Info ARM64Utils Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target
add_to_library_groups = ARM64
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h b/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h
index 7717743..553ddae 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h
@@ -164,64 +164,6 @@ static inline unsigned getMemExtendImm(ARM64_AM::ExtendType ET, bool DoShift) {
return (unsigned(ET) << 1) | unsigned(DoShift);
}
-//===----------------------------------------------------------------------===//
-// Prefetch
-//
-
-/// Pre-fetch operator names.
-/// The enum values match the encoding values:
-/// prfop<4:3> 00=preload data, 10=prepare for store
-/// prfop<2:1> 00=target L1 cache, 01=target L2 cache, 10=target L3 cache,
-/// prfop<0> 0=non-streaming (temporal), 1=streaming (non-temporal)
-enum PrefetchOp {
- InvalidPrefetchOp = -1,
- PLDL1KEEP = 0x00,
- PLDL1STRM = 0x01,
- PLDL2KEEP = 0x02,
- PLDL2STRM = 0x03,
- PLDL3KEEP = 0x04,
- PLDL3STRM = 0x05,
- PSTL1KEEP = 0x10,
- PSTL1STRM = 0x11,
- PSTL2KEEP = 0x12,
- PSTL2STRM = 0x13,
- PSTL3KEEP = 0x14,
- PSTL3STRM = 0x15
-};
-
-/// isNamedPrefetchOp - Check if the prefetch-op 5-bit value has a name.
-static inline bool isNamedPrefetchOp(unsigned prfop) {
- switch (prfop) {
- default: return false;
- case ARM64_AM::PLDL1KEEP: case ARM64_AM::PLDL1STRM: case ARM64_AM::PLDL2KEEP:
- case ARM64_AM::PLDL2STRM: case ARM64_AM::PLDL3KEEP: case ARM64_AM::PLDL3STRM:
- case ARM64_AM::PSTL1KEEP: case ARM64_AM::PSTL1STRM: case ARM64_AM::PSTL2KEEP:
- case ARM64_AM::PSTL2STRM: case ARM64_AM::PSTL3KEEP: case ARM64_AM::PSTL3STRM:
- return true;
- }
-}
-
-
-/// getPrefetchOpName - Get the string encoding for the prefetch operator.
-static inline const char *getPrefetchOpName(ARM64_AM::PrefetchOp prfop) {
- switch (prfop) {
- default: assert(false && "unhandled prefetch-op type!");
- case ARM64_AM::PLDL1KEEP: return "pldl1keep";
- case ARM64_AM::PLDL1STRM: return "pldl1strm";
- case ARM64_AM::PLDL2KEEP: return "pldl2keep";
- case ARM64_AM::PLDL2STRM: return "pldl2strm";
- case ARM64_AM::PLDL3KEEP: return "pldl3keep";
- case ARM64_AM::PLDL3STRM: return "pldl3strm";
- case ARM64_AM::PSTL1KEEP: return "pstl1keep";
- case ARM64_AM::PSTL1STRM: return "pstl1strm";
- case ARM64_AM::PSTL2KEEP: return "pstl2keep";
- case ARM64_AM::PSTL2STRM: return "pstl2strm";
- case ARM64_AM::PSTL3KEEP: return "pstl3keep";
- case ARM64_AM::PSTL3STRM: return "pstl3strm";
- }
- return 0;
-}
-
static inline uint64_t ror(uint64_t elt, unsigned size) {
return ((elt & 1) << (size-1)) | (elt >> 1);
}
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h b/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h
deleted file mode 100644
index d3c2cf7..0000000
--- a/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h
+++ /dev/null
@@ -1,998 +0,0 @@
-//===-- ARM64BaseInfo.h - Top level definitions for ARM64 -------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains small standalone helper functions and enum definitions for
-// the ARM64 target useful for the compiler back-end and the MC libraries.
-// As such, it deliberately does not include references to LLVM core
-// code gen types, passes, etc..
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ARM64BASEINFO_H
-#define ARM64BASEINFO_H
-
-#include "ARM64MCTargetDesc.h"
-#include "llvm/Support/ErrorHandling.h"
-
-namespace llvm {
-
-inline static unsigned getWRegFromXReg(unsigned Reg) {
- switch (Reg) {
- case ARM64::X0: return ARM64::W0;
- case ARM64::X1: return ARM64::W1;
- case ARM64::X2: return ARM64::W2;
- case ARM64::X3: return ARM64::W3;
- case ARM64::X4: return ARM64::W4;
- case ARM64::X5: return ARM64::W5;
- case ARM64::X6: return ARM64::W6;
- case ARM64::X7: return ARM64::W7;
- case ARM64::X8: return ARM64::W8;
- case ARM64::X9: return ARM64::W9;
- case ARM64::X10: return ARM64::W10;
- case ARM64::X11: return ARM64::W11;
- case ARM64::X12: return ARM64::W12;
- case ARM64::X13: return ARM64::W13;
- case ARM64::X14: return ARM64::W14;
- case ARM64::X15: return ARM64::W15;
- case ARM64::X16: return ARM64::W16;
- case ARM64::X17: return ARM64::W17;
- case ARM64::X18: return ARM64::W18;
- case ARM64::X19: return ARM64::W19;
- case ARM64::X20: return ARM64::W20;
- case ARM64::X21: return ARM64::W21;
- case ARM64::X22: return ARM64::W22;
- case ARM64::X23: return ARM64::W23;
- case ARM64::X24: return ARM64::W24;
- case ARM64::X25: return ARM64::W25;
- case ARM64::X26: return ARM64::W26;
- case ARM64::X27: return ARM64::W27;
- case ARM64::X28: return ARM64::W28;
- case ARM64::FP: return ARM64::W29;
- case ARM64::LR: return ARM64::W30;
- case ARM64::SP: return ARM64::WSP;
- case ARM64::XZR: return ARM64::WZR;
- }
- // For anything else, return it unchanged.
- return Reg;
-}
-
-inline static unsigned getXRegFromWReg(unsigned Reg) {
- switch (Reg) {
- case ARM64::W0: return ARM64::X0;
- case ARM64::W1: return ARM64::X1;
- case ARM64::W2: return ARM64::X2;
- case ARM64::W3: return ARM64::X3;
- case ARM64::W4: return ARM64::X4;
- case ARM64::W5: return ARM64::X5;
- case ARM64::W6: return ARM64::X6;
- case ARM64::W7: return ARM64::X7;
- case ARM64::W8: return ARM64::X8;
- case ARM64::W9: return ARM64::X9;
- case ARM64::W10: return ARM64::X10;
- case ARM64::W11: return ARM64::X11;
- case ARM64::W12: return ARM64::X12;
- case ARM64::W13: return ARM64::X13;
- case ARM64::W14: return ARM64::X14;
- case ARM64::W15: return ARM64::X15;
- case ARM64::W16: return ARM64::X16;
- case ARM64::W17: return ARM64::X17;
- case ARM64::W18: return ARM64::X18;
- case ARM64::W19: return ARM64::X19;
- case ARM64::W20: return ARM64::X20;
- case ARM64::W21: return ARM64::X21;
- case ARM64::W22: return ARM64::X22;
- case ARM64::W23: return ARM64::X23;
- case ARM64::W24: return ARM64::X24;
- case ARM64::W25: return ARM64::X25;
- case ARM64::W26: return ARM64::X26;
- case ARM64::W27: return ARM64::X27;
- case ARM64::W28: return ARM64::X28;
- case ARM64::W29: return ARM64::FP;
- case ARM64::W30: return ARM64::LR;
- case ARM64::WSP: return ARM64::SP;
- case ARM64::WZR: return ARM64::XZR;
- }
- // For anything else, return it unchanged.
- return Reg;
-}
-
-static inline unsigned getBRegFromDReg(unsigned Reg) {
- switch (Reg) {
- case ARM64::D0: return ARM64::B0;
- case ARM64::D1: return ARM64::B1;
- case ARM64::D2: return ARM64::B2;
- case ARM64::D3: return ARM64::B3;
- case ARM64::D4: return ARM64::B4;
- case ARM64::D5: return ARM64::B5;
- case ARM64::D6: return ARM64::B6;
- case ARM64::D7: return ARM64::B7;
- case ARM64::D8: return ARM64::B8;
- case ARM64::D9: return ARM64::B9;
- case ARM64::D10: return ARM64::B10;
- case ARM64::D11: return ARM64::B11;
- case ARM64::D12: return ARM64::B12;
- case ARM64::D13: return ARM64::B13;
- case ARM64::D14: return ARM64::B14;
- case ARM64::D15: return ARM64::B15;
- case ARM64::D16: return ARM64::B16;
- case ARM64::D17: return ARM64::B17;
- case ARM64::D18: return ARM64::B18;
- case ARM64::D19: return ARM64::B19;
- case ARM64::D20: return ARM64::B20;
- case ARM64::D21: return ARM64::B21;
- case ARM64::D22: return ARM64::B22;
- case ARM64::D23: return ARM64::B23;
- case ARM64::D24: return ARM64::B24;
- case ARM64::D25: return ARM64::B25;
- case ARM64::D26: return ARM64::B26;
- case ARM64::D27: return ARM64::B27;
- case ARM64::D28: return ARM64::B28;
- case ARM64::D29: return ARM64::B29;
- case ARM64::D30: return ARM64::B30;
- case ARM64::D31: return ARM64::B31;
- }
- // For anything else, return it unchanged.
- return Reg;
-}
-
-
-static inline unsigned getDRegFromBReg(unsigned Reg) {
- switch (Reg) {
- case ARM64::B0: return ARM64::D0;
- case ARM64::B1: return ARM64::D1;
- case ARM64::B2: return ARM64::D2;
- case ARM64::B3: return ARM64::D3;
- case ARM64::B4: return ARM64::D4;
- case ARM64::B5: return ARM64::D5;
- case ARM64::B6: return ARM64::D6;
- case ARM64::B7: return ARM64::D7;
- case ARM64::B8: return ARM64::D8;
- case ARM64::B9: return ARM64::D9;
- case ARM64::B10: return ARM64::D10;
- case ARM64::B11: return ARM64::D11;
- case ARM64::B12: return ARM64::D12;
- case ARM64::B13: return ARM64::D13;
- case ARM64::B14: return ARM64::D14;
- case ARM64::B15: return ARM64::D15;
- case ARM64::B16: return ARM64::D16;
- case ARM64::B17: return ARM64::D17;
- case ARM64::B18: return ARM64::D18;
- case ARM64::B19: return ARM64::D19;
- case ARM64::B20: return ARM64::D20;
- case ARM64::B21: return ARM64::D21;
- case ARM64::B22: return ARM64::D22;
- case ARM64::B23: return ARM64::D23;
- case ARM64::B24: return ARM64::D24;
- case ARM64::B25: return ARM64::D25;
- case ARM64::B26: return ARM64::D26;
- case ARM64::B27: return ARM64::D27;
- case ARM64::B28: return ARM64::D28;
- case ARM64::B29: return ARM64::D29;
- case ARM64::B30: return ARM64::D30;
- case ARM64::B31: return ARM64::D31;
- }
- // For anything else, return it unchanged.
- return Reg;
-}
-
-namespace ARM64CC {
-
-// The CondCodes constants map directly to the 4-bit encoding of the condition
-// field for predicated instructions.
-enum CondCode { // Meaning (integer) Meaning (floating-point)
- EQ = 0x0, // Equal Equal
- NE = 0x1, // Not equal Not equal, or unordered
- CS = 0x2, // Carry set >, ==, or unordered
- CC = 0x3, // Carry clear Less than
- MI = 0x4, // Minus, negative Less than
- PL = 0x5, // Plus, positive or zero >, ==, or unordered
- VS = 0x6, // Overflow Unordered
- VC = 0x7, // No overflow Not unordered
- HI = 0x8, // Unsigned higher Greater than, or unordered
- LS = 0x9, // Unsigned lower or same Less than or equal
- GE = 0xa, // Greater than or equal Greater than or equal
- LT = 0xb, // Less than Less than, or unordered
- GT = 0xc, // Greater than Greater than
- LE = 0xd, // Less than or equal <, ==, or unordered
- AL = 0xe // Always (unconditional) Always (unconditional)
-};
-
-inline static const char *getCondCodeName(CondCode Code) {
- // cond<0> is ignored when cond<3:1> = 111, where 1110 is 0xe (aka AL).
- if ((Code & AL) == AL)
- Code = AL;
- switch (Code) {
- case EQ: return "eq";
- case NE: return "ne";
- case CS: return "cs";
- case CC: return "cc";
- case MI: return "mi";
- case PL: return "pl";
- case VS: return "vs";
- case VC: return "vc";
- case HI: return "hi";
- case LS: return "ls";
- case GE: return "ge";
- case LT: return "lt";
- case GT: return "gt";
- case LE: return "le";
- case AL: return "al";
- }
- llvm_unreachable("Unknown condition code");
-}
-
-inline static CondCode getInvertedCondCode(CondCode Code) {
- switch (Code) {
- default: llvm_unreachable("Unknown condition code");
- case EQ: return NE;
- case NE: return EQ;
- case CS: return CC;
- case CC: return CS;
- case MI: return PL;
- case PL: return MI;
- case VS: return VC;
- case VC: return VS;
- case HI: return LS;
- case LS: return HI;
- case GE: return LT;
- case LT: return GE;
- case GT: return LE;
- case LE: return GT;
- }
-}
-
-/// Given a condition code, return NZCV flags that would satisfy that condition.
-/// The flag bits are in the format expected by the ccmp instructions.
-/// Note that many different flag settings can satisfy a given condition code,
-/// this function just returns one of them.
-inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
- // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
- enum { N = 8, Z = 4, C = 2, V = 1 };
- switch (Code) {
- default: llvm_unreachable("Unknown condition code");
- case EQ: return Z; // Z == 1
- case NE: return 0; // Z == 0
- case CS: return C; // C == 1
- case CC: return 0; // C == 0
- case MI: return N; // N == 1
- case PL: return 0; // N == 0
- case VS: return V; // V == 1
- case VC: return 0; // V == 0
- case HI: return C; // C == 1 && Z == 0
- case LS: return 0; // C == 0 || Z == 1
- case GE: return 0; // N == V
- case LT: return N; // N != V
- case GT: return 0; // Z == 0 && N == V
- case LE: return Z; // Z == 1 || N != V
- }
-}
-} // end namespace ARM64CC
-
-namespace ARM64SYS {
-enum BarrierOption {
- InvalidBarrier = 0xff,
- OSHLD = 0x1,
- OSHST = 0x2,
- OSH = 0x3,
- NSHLD = 0x5,
- NSHST = 0x6,
- NSH = 0x7,
- ISHLD = 0x9,
- ISHST = 0xa,
- ISH = 0xb,
- LD = 0xd,
- ST = 0xe,
- SY = 0xf
-};
-
-inline static const char *getBarrierOptName(BarrierOption Opt) {
- switch (Opt) {
- default: return NULL;
- case 0x1: return "oshld";
- case 0x2: return "oshst";
- case 0x3: return "osh";
- case 0x5: return "nshld";
- case 0x6: return "nshst";
- case 0x7: return "nsh";
- case 0x9: return "ishld";
- case 0xa: return "ishst";
- case 0xb: return "ish";
- case 0xd: return "ld";
- case 0xe: return "st";
- case 0xf: return "sy";
- }
-}
-
-#define A64_SYSREG_ENC(op0,CRn,op2,CRm,op1) ((op0) << 14 | (op1) << 11 | \
- (CRn) << 7 | (CRm) << 3 | (op2))
-enum SystemRegister {
- InvalidSystemReg = 0,
- // Table in section 3.10.3
- SPSR_EL1 = 0xc200,
- SPSR_svc = SPSR_EL1,
- ELR_EL1 = 0xc201,
- SP_EL0 = 0xc208,
- SPSel = 0xc210,
- CurrentEL = 0xc212,
- DAIF = 0xda11,
- NZCV = 0xda10,
- FPCR = 0xda20,
- FPSR = 0xda21,
- DSPSR = 0xda28,
- DLR = 0xda29,
- SPSR_EL2 = 0xe200,
- SPSR_hyp = SPSR_EL2,
- ELR_EL2 = 0xe201,
- SP_EL1 = 0xe208,
- SPSR_irq = 0xe218,
- SPSR_abt = 0xe219,
- SPSR_und = 0xe21a,
- SPSR_fiq = 0xe21b,
- SPSR_EL3 = 0xf200,
- ELR_EL3 = 0xf201,
- SP_EL2 = 0xf208,
-
-
- // Table in section 3.10.8
- MIDR_EL1 = 0xc000,
- CTR_EL0 = 0xd801,
- MPIDR_EL1 = 0xc005,
- ECOIDR_EL1 = 0xc006,
- DCZID_EL0 = 0xd807,
- MVFR0_EL1 = 0xc018,
- MVFR1_EL1 = 0xc019,
- ID_AA64PFR0_EL1 = 0xc020,
- ID_AA64PFR1_EL1 = 0xc021,
- ID_AA64DFR0_EL1 = 0xc028,
- ID_AA64DFR1_EL1 = 0xc029,
- ID_AA64ISAR0_EL1 = 0xc030,
- ID_AA64ISAR1_EL1 = 0xc031,
- ID_AA64MMFR0_EL1 = 0xc038,
- ID_AA64MMFR1_EL1 = 0xc039,
- CCSIDR_EL1 = 0xc800,
- CLIDR_EL1 = 0xc801,
- AIDR_EL1 = 0xc807,
- CSSELR_EL1 = 0xd000,
- VPIDR_EL2 = 0xe000,
- VMPIDR_EL2 = 0xe005,
- SCTLR_EL1 = 0xc080,
- SCTLR_EL2 = 0xe080,
- SCTLR_EL3 = 0xf080,
- ACTLR_EL1 = 0xc081,
- ACTLR_EL2 = 0xe081,
- ACTLR_EL3 = 0xf081,
- CPACR_EL1 = 0xc082,
- CPTR_EL2 = 0xe08a,
- CPTR_EL3 = 0xf08a,
- SCR_EL3 = 0xf088,
- HCR_EL2 = 0xe088,
- MDCR_EL2 = 0xe089,
- MDCR_EL3 = 0xf099,
- HSTR_EL2 = 0xe08b,
- HACR_EL2 = 0xe08f,
- TTBR0_EL1 = 0xc100,
- TTBR1_EL1 = 0xc101,
- TTBR0_EL2 = 0xe100,
- TTBR0_EL3 = 0xf100,
- VTTBR_EL2 = 0xe108,
- TCR_EL1 = 0xc102,
- TCR_EL2 = 0xe102,
- TCR_EL3 = 0xf102,
- VTCR_EL2 = 0xe10a,
- ADFSR_EL1 = 0xc288,
- AIFSR_EL1 = 0xc289,
- ADFSR_EL2 = 0xe288,
- AIFSR_EL2 = 0xe289,
- ADFSR_EL3 = 0xf288,
- AIFSR_EL3 = 0xf289,
- ESR_EL1 = 0xc290,
- ESR_EL2 = 0xe290,
- ESR_EL3 = 0xf290,
- FAR_EL1 = 0xc300,
- FAR_EL2 = 0xe300,
- FAR_EL3 = 0xf300,
- HPFAR_EL2 = 0xe304,
- PAR_EL1 = 0xc3a0,
- MAIR_EL1 = 0xc510,
- MAIR_EL2 = 0xe510,
- MAIR_EL3 = 0xf510,
- AMAIR_EL1 = 0xc518,
- AMAIR_EL2 = 0xe518,
- AMAIR_EL3 = 0xf518,
- VBAR_EL1 = 0xc600,
- VBAR_EL2 = 0xe600,
- VBAR_EL3 = 0xf600,
- RVBAR_EL1 = 0xc601,
- RVBAR_EL2 = 0xe601,
- RVBAR_EL3 = 0xf601,
- ISR_EL1 = 0xc608,
- CONTEXTIDR_EL1 = 0xc681,
- TPIDR_EL0 = 0xde82,
- TPIDRRO_EL0 = 0xde83,
- TPIDR_EL1 = 0xc684,
- TPIDR_EL2 = 0xe682,
- TPIDR_EL3 = 0xf682,
- TEECR32_EL1 = 0x9000,
- CNTFRQ_EL0 = 0xdf00,
- CNTPCT_EL0 = 0xdf01,
- CNTVCT_EL0 = 0xdf02,
- CNTVOFF_EL2 = 0xe703,
- CNTKCTL_EL1 = 0xc708,
- CNTHCTL_EL2 = 0xe708,
- CNTP_TVAL_EL0 = 0xdf10,
- CNTP_CTL_EL0 = 0xdf11,
- CNTP_CVAL_EL0 = 0xdf12,
- CNTV_TVAL_EL0 = 0xdf18,
- CNTV_CTL_EL0 = 0xdf19,
- CNTV_CVAL_EL0 = 0xdf1a,
- CNTHP_TVAL_EL2 = 0xe710,
- CNTHP_CTL_EL2 = 0xe711,
- CNTHP_CVAL_EL2 = 0xe712,
- CNTPS_TVAL_EL1 = 0xff10,
- CNTPS_CTL_EL1 = 0xff11,
- CNTPS_CVAL_EL1= 0xff12,
-
- PMEVCNTR0_EL0 = 0xdf40,
- PMEVCNTR1_EL0 = 0xdf41,
- PMEVCNTR2_EL0 = 0xdf42,
- PMEVCNTR3_EL0 = 0xdf43,
- PMEVCNTR4_EL0 = 0xdf44,
- PMEVCNTR5_EL0 = 0xdf45,
- PMEVCNTR6_EL0 = 0xdf46,
- PMEVCNTR7_EL0 = 0xdf47,
- PMEVCNTR8_EL0 = 0xdf48,
- PMEVCNTR9_EL0 = 0xdf49,
- PMEVCNTR10_EL0 = 0xdf4a,
- PMEVCNTR11_EL0 = 0xdf4b,
- PMEVCNTR12_EL0 = 0xdf4c,
- PMEVCNTR13_EL0 = 0xdf4d,
- PMEVCNTR14_EL0 = 0xdf4e,
- PMEVCNTR15_EL0 = 0xdf4f,
- PMEVCNTR16_EL0 = 0xdf50,
- PMEVCNTR17_EL0 = 0xdf51,
- PMEVCNTR18_EL0 = 0xdf52,
- PMEVCNTR19_EL0 = 0xdf53,
- PMEVCNTR20_EL0 = 0xdf54,
- PMEVCNTR21_EL0 = 0xdf55,
- PMEVCNTR22_EL0 = 0xdf56,
- PMEVCNTR23_EL0 = 0xdf57,
- PMEVCNTR24_EL0 = 0xdf58,
- PMEVCNTR25_EL0 = 0xdf59,
- PMEVCNTR26_EL0 = 0xdf5a,
- PMEVCNTR27_EL0 = 0xdf5b,
- PMEVCNTR28_EL0 = 0xdf5c,
- PMEVCNTR29_EL0 = 0xdf5d,
- PMEVCNTR30_EL0 = 0xdf5e,
-
- PMEVTYPER0_EL0 = 0xdf60,
- PMEVTYPER1_EL0 = 0xdf61,
- PMEVTYPER2_EL0 = 0xdf62,
- PMEVTYPER3_EL0 = 0xdf63,
- PMEVTYPER4_EL0 = 0xdf64,
- PMEVTYPER5_EL0 = 0xdf65,
- PMEVTYPER6_EL0 = 0xdf66,
- PMEVTYPER7_EL0 = 0xdf67,
- PMEVTYPER8_EL0 = 0xdf68,
- PMEVTYPER9_EL0 = 0xdf69,
- PMEVTYPER10_EL0 = 0xdf6a,
- PMEVTYPER11_EL0 = 0xdf6b,
- PMEVTYPER12_EL0 = 0xdf6c,
- PMEVTYPER13_EL0 = 0xdf6d,
- PMEVTYPER14_EL0 = 0xdf6e,
- PMEVTYPER15_EL0 = 0xdf6f,
- PMEVTYPER16_EL0 = 0xdf70,
- PMEVTYPER17_EL0 = 0xdf71,
- PMEVTYPER18_EL0 = 0xdf72,
- PMEVTYPER19_EL0 = 0xdf73,
- PMEVTYPER20_EL0 = 0xdf74,
- PMEVTYPER21_EL0 = 0xdf75,
- PMEVTYPER22_EL0 = 0xdf76,
- PMEVTYPER23_EL0 = 0xdf77,
- PMEVTYPER24_EL0 = 0xdf78,
- PMEVTYPER25_EL0 = 0xdf79,
- PMEVTYPER26_EL0 = 0xdf7a,
- PMEVTYPER27_EL0 = 0xdf7b,
- PMEVTYPER28_EL0 = 0xdf7c,
- PMEVTYPER29_EL0 = 0xdf7d,
- PMEVTYPER30_EL0 = 0xdf7e,
-
- PMCCFILTR_EL0 = 0xdf7f,
-
- RMR_EL3 = 0xf602,
- RMR_EL2 = 0xd602,
- RMR_EL1 = 0xce02,
-
- // Debug Architecture 5.3, Table 17.
- MDCCSR_EL0 = A64_SYSREG_ENC(2, 0, 0, 1, 3),
- MDCCINT_EL1 = A64_SYSREG_ENC(2, 0, 0, 2, 0),
- DBGDTR_EL0 = A64_SYSREG_ENC(2, 0, 0, 4, 3),
- DBGDTRRX_EL0 = A64_SYSREG_ENC(2, 0, 0, 5, 3),
- DBGDTRTX_EL0 = DBGDTRRX_EL0,
- DBGVCR32_EL2 = A64_SYSREG_ENC(2, 0, 0, 7, 4),
- OSDTRRX_EL1 = A64_SYSREG_ENC(2, 0, 2, 0, 0),
- MDSCR_EL1 = A64_SYSREG_ENC(2, 0, 2, 2, 0),
- OSDTRTX_EL1 = A64_SYSREG_ENC(2, 0, 2, 3, 0),
- OSECCR_EL11 = A64_SYSREG_ENC(2, 0, 2, 6, 0),
-
- DBGBVR0_EL1 = A64_SYSREG_ENC(2, 0, 4, 0, 0),
- DBGBVR1_EL1 = A64_SYSREG_ENC(2, 0, 4, 1, 0),
- DBGBVR2_EL1 = A64_SYSREG_ENC(2, 0, 4, 2, 0),
- DBGBVR3_EL1 = A64_SYSREG_ENC(2, 0, 4, 3, 0),
- DBGBVR4_EL1 = A64_SYSREG_ENC(2, 0, 4, 4, 0),
- DBGBVR5_EL1 = A64_SYSREG_ENC(2, 0, 4, 5, 0),
- DBGBVR6_EL1 = A64_SYSREG_ENC(2, 0, 4, 6, 0),
- DBGBVR7_EL1 = A64_SYSREG_ENC(2, 0, 4, 7, 0),
- DBGBVR8_EL1 = A64_SYSREG_ENC(2, 0, 4, 8, 0),
- DBGBVR9_EL1 = A64_SYSREG_ENC(2, 0, 4, 9, 0),
- DBGBVR10_EL1 = A64_SYSREG_ENC(2, 0, 4, 10, 0),
- DBGBVR11_EL1 = A64_SYSREG_ENC(2, 0, 4, 11, 0),
- DBGBVR12_EL1 = A64_SYSREG_ENC(2, 0, 4, 12, 0),
- DBGBVR13_EL1 = A64_SYSREG_ENC(2, 0, 4, 13, 0),
- DBGBVR14_EL1 = A64_SYSREG_ENC(2, 0, 4, 14, 0),
- DBGBVR15_EL1 = A64_SYSREG_ENC(2, 0, 4, 15, 0),
-
- DBGBCR0_EL1 = A64_SYSREG_ENC(2, 0, 5, 0, 0),
- DBGBCR1_EL1 = A64_SYSREG_ENC(2, 0, 5, 1, 0),
- DBGBCR2_EL1 = A64_SYSREG_ENC(2, 0, 5, 2, 0),
- DBGBCR3_EL1 = A64_SYSREG_ENC(2, 0, 5, 3, 0),
- DBGBCR4_EL1 = A64_SYSREG_ENC(2, 0, 5, 4, 0),
- DBGBCR5_EL1 = A64_SYSREG_ENC(2, 0, 5, 5, 0),
- DBGBCR6_EL1 = A64_SYSREG_ENC(2, 0, 5, 6, 0),
- DBGBCR7_EL1 = A64_SYSREG_ENC(2, 0, 5, 7, 0),
- DBGBCR8_EL1 = A64_SYSREG_ENC(2, 0, 5, 8, 0),
- DBGBCR9_EL1 = A64_SYSREG_ENC(2, 0, 5, 9, 0),
- DBGBCR10_EL1 = A64_SYSREG_ENC(2, 0, 5, 10, 0),
- DBGBCR11_EL1 = A64_SYSREG_ENC(2, 0, 5, 11, 0),
- DBGBCR12_EL1 = A64_SYSREG_ENC(2, 0, 5, 12, 0),
- DBGBCR13_EL1 = A64_SYSREG_ENC(2, 0, 5, 13, 0),
- DBGBCR14_EL1 = A64_SYSREG_ENC(2, 0, 5, 14, 0),
- DBGBCR15_EL1 = A64_SYSREG_ENC(2, 0, 5, 15, 0),
-
- DBGWVR0_EL1 = A64_SYSREG_ENC(2, 0, 6, 0, 0),
- DBGWVR1_EL1 = A64_SYSREG_ENC(2, 0, 6, 1, 0),
- DBGWVR2_EL1 = A64_SYSREG_ENC(2, 0, 6, 2, 0),
- DBGWVR3_EL1 = A64_SYSREG_ENC(2, 0, 6, 3, 0),
- DBGWVR4_EL1 = A64_SYSREG_ENC(2, 0, 6, 4, 0),
- DBGWVR5_EL1 = A64_SYSREG_ENC(2, 0, 6, 5, 0),
- DBGWVR6_EL1 = A64_SYSREG_ENC(2, 0, 6, 6, 0),
- DBGWVR7_EL1 = A64_SYSREG_ENC(2, 0, 6, 7, 0),
- DBGWVR8_EL1 = A64_SYSREG_ENC(2, 0, 6, 8, 0),
- DBGWVR9_EL1 = A64_SYSREG_ENC(2, 0, 6, 9, 0),
- DBGWVR10_EL1 = A64_SYSREG_ENC(2, 0, 6, 10, 0),
- DBGWVR11_EL1 = A64_SYSREG_ENC(2, 0, 6, 11, 0),
- DBGWVR12_EL1 = A64_SYSREG_ENC(2, 0, 6, 12, 0),
- DBGWVR13_EL1 = A64_SYSREG_ENC(2, 0, 6, 13, 0),
- DBGWVR14_EL1 = A64_SYSREG_ENC(2, 0, 6, 14, 0),
- DBGWVR15_EL1 = A64_SYSREG_ENC(2, 0, 6, 15, 0),
-
- DBGWCR0_EL1 = A64_SYSREG_ENC(2, 0, 7, 0, 0),
- DBGWCR1_EL1 = A64_SYSREG_ENC(2, 0, 7, 1, 0),
- DBGWCR2_EL1 = A64_SYSREG_ENC(2, 0, 7, 2, 0),
- DBGWCR3_EL1 = A64_SYSREG_ENC(2, 0, 7, 3, 0),
- DBGWCR4_EL1 = A64_SYSREG_ENC(2, 0, 7, 4, 0),
- DBGWCR5_EL1 = A64_SYSREG_ENC(2, 0, 7, 5, 0),
- DBGWCR6_EL1 = A64_SYSREG_ENC(2, 0, 7, 6, 0),
- DBGWCR7_EL1 = A64_SYSREG_ENC(2, 0, 7, 7, 0),
- DBGWCR8_EL1 = A64_SYSREG_ENC(2, 0, 7, 8, 0),
- DBGWCR9_EL1 = A64_SYSREG_ENC(2, 0, 7, 9, 0),
- DBGWCR10_EL1 = A64_SYSREG_ENC(2, 0, 7, 10, 0),
- DBGWCR11_EL1 = A64_SYSREG_ENC(2, 0, 7, 11, 0),
- DBGWCR12_EL1 = A64_SYSREG_ENC(2, 0, 7, 12, 0),
- DBGWCR13_EL1 = A64_SYSREG_ENC(2, 0, 7, 13, 0),
- DBGWCR14_EL1 = A64_SYSREG_ENC(2, 0, 7, 14, 0),
- DBGWCR15_EL1 = A64_SYSREG_ENC(2, 0, 7, 15, 0),
-
- MDRAR_EL1 = A64_SYSREG_ENC(2, 1, 0, 0, 0),
- OSLAR_EL1 = A64_SYSREG_ENC(2, 1, 4, 0, 0),
- OSLSR_EL1 = A64_SYSREG_ENC(2, 1, 4, 1, 0),
- OSDLR_EL1 = A64_SYSREG_ENC(2, 1, 4, 3, 0),
- DBGPRCR_EL1 = A64_SYSREG_ENC(2, 1, 4, 4, 0),
-
- DBGCLAIMSET_EL1 = A64_SYSREG_ENC(2, 7, 6, 8, 0),
- DBGCLAIMCLR_EL1 = A64_SYSREG_ENC(2, 7, 6, 9, 0),
- DBGAUTHSTATUS_EL1 = A64_SYSREG_ENC(2, 7, 6, 14, 0),
-
- DBGDEVID2 = A64_SYSREG_ENC(2, 7, 7, 0, 0),
- DBGDEVID1 = A64_SYSREG_ENC(2, 7, 7, 1, 0),
- DBGDEVID0 = A64_SYSREG_ENC(2, 7, 7, 2, 0),
-
- // The following registers are defined to allow access from AArch64 to
- // registers which are only used in the AArch32 architecture.
- DACR32_EL2 = 0xe180,
- IFSR32_EL2 = 0xe281,
- TEEHBR32_EL1 = 0x9080,
- SDER32_EL3 = 0xf089,
- FPEXC32_EL2 = 0xe298,
-
- // Cyclone specific system registers
- CPM_IOACC_CTL_EL3 = 0xff90,
-
- // Architectural system registers
- ID_PFR0_EL1 = 0xc008,
- ID_PFR1_EL1 = 0xc009,
- ID_DFR0_EL1 = 0xc00a,
- ID_AFR0_EL1 = 0xc00b,
- ID_ISAR0_EL1 = 0xc010,
- ID_ISAR1_EL1 = 0xc011,
- ID_ISAR2_EL1 = 0xc012,
- ID_ISAR3_EL1 = 0xc013,
- ID_ISAR4_EL1 = 0xc014,
- ID_ISAR5_EL1 = 0xc015,
- AFSR1_EL1 = 0xc289, // note same as old AIFSR_EL1
- AFSR0_EL1 = 0xc288, // note same as old ADFSR_EL1
- REVIDR_EL1 = 0xc006 // note same as old ECOIDR_EL1
-
-};
-#undef A64_SYSREG_ENC
-
-static inline const char *getSystemRegisterName(SystemRegister Reg) {
- switch(Reg) {
- default: return NULL; // Caller is responsible for handling invalid value.
- case SPSR_EL1: return "SPSR_EL1";
- case ELR_EL1: return "ELR_EL1";
- case SP_EL0: return "SP_EL0";
- case SPSel: return "SPSel";
- case DAIF: return "DAIF";
- case CurrentEL: return "CurrentEL";
- case NZCV: return "NZCV";
- case FPCR: return "FPCR";
- case FPSR: return "FPSR";
- case DSPSR: return "DSPSR";
- case DLR: return "DLR";
- case SPSR_EL2: return "SPSR_EL2";
- case ELR_EL2: return "ELR_EL2";
- case SP_EL1: return "SP_EL1";
- case SPSR_irq: return "SPSR_irq";
- case SPSR_abt: return "SPSR_abt";
- case SPSR_und: return "SPSR_und";
- case SPSR_fiq: return "SPSR_fiq";
- case SPSR_EL3: return "SPSR_EL3";
- case ELR_EL3: return "ELR_EL3";
- case SP_EL2: return "SP_EL2";
- case MIDR_EL1: return "MIDR_EL1";
- case CTR_EL0: return "CTR_EL0";
- case MPIDR_EL1: return "MPIDR_EL1";
- case DCZID_EL0: return "DCZID_EL0";
- case MVFR0_EL1: return "MVFR0_EL1";
- case MVFR1_EL1: return "MVFR1_EL1";
- case ID_AA64PFR0_EL1: return "ID_AA64PFR0_EL1";
- case ID_AA64PFR1_EL1: return "ID_AA64PFR1_EL1";
- case ID_AA64DFR0_EL1: return "ID_AA64DFR0_EL1";
- case ID_AA64DFR1_EL1: return "ID_AA64DFR1_EL1";
- case ID_AA64ISAR0_EL1: return "ID_AA64ISAR0_EL1";
- case ID_AA64ISAR1_EL1: return "ID_AA64ISAR1_EL1";
- case ID_AA64MMFR0_EL1: return "ID_AA64MMFR0_EL1";
- case ID_AA64MMFR1_EL1: return "ID_AA64MMFR1_EL1";
- case CCSIDR_EL1: return "CCSIDR_EL1";
- case CLIDR_EL1: return "CLIDR_EL1";
- case AIDR_EL1: return "AIDR_EL1";
- case CSSELR_EL1: return "CSSELR_EL1";
- case VPIDR_EL2: return "VPIDR_EL2";
- case VMPIDR_EL2: return "VMPIDR_EL2";
- case SCTLR_EL1: return "SCTLR_EL1";
- case SCTLR_EL2: return "SCTLR_EL2";
- case SCTLR_EL3: return "SCTLR_EL3";
- case ACTLR_EL1: return "ACTLR_EL1";
- case ACTLR_EL2: return "ACTLR_EL2";
- case ACTLR_EL3: return "ACTLR_EL3";
- case CPACR_EL1: return "CPACR_EL1";
- case CPTR_EL2: return "CPTR_EL2";
- case CPTR_EL3: return "CPTR_EL3";
- case SCR_EL3: return "SCR_EL3";
- case HCR_EL2: return "HCR_EL2";
- case MDCR_EL2: return "MDCR_EL2";
- case MDCR_EL3: return "MDCR_EL3";
- case HSTR_EL2: return "HSTR_EL2";
- case HACR_EL2: return "HACR_EL2";
- case TTBR0_EL1: return "TTBR0_EL1";
- case TTBR1_EL1: return "TTBR1_EL1";
- case TTBR0_EL2: return "TTBR0_EL2";
- case TTBR0_EL3: return "TTBR0_EL3";
- case VTTBR_EL2: return "VTTBR_EL2";
- case TCR_EL1: return "TCR_EL1";
- case TCR_EL2: return "TCR_EL2";
- case TCR_EL3: return "TCR_EL3";
- case VTCR_EL2: return "VTCR_EL2";
- case ADFSR_EL2: return "ADFSR_EL2";
- case AIFSR_EL2: return "AIFSR_EL2";
- case ADFSR_EL3: return "ADFSR_EL3";
- case AIFSR_EL3: return "AIFSR_EL3";
- case ESR_EL1: return "ESR_EL1";
- case ESR_EL2: return "ESR_EL2";
- case ESR_EL3: return "ESR_EL3";
- case FAR_EL1: return "FAR_EL1";
- case FAR_EL2: return "FAR_EL2";
- case FAR_EL3: return "FAR_EL3";
- case HPFAR_EL2: return "HPFAR_EL2";
- case PAR_EL1: return "PAR_EL1";
- case MAIR_EL1: return "MAIR_EL1";
- case MAIR_EL2: return "MAIR_EL2";
- case MAIR_EL3: return "MAIR_EL3";
- case AMAIR_EL1: return "AMAIR_EL1";
- case AMAIR_EL2: return "AMAIR_EL2";
- case AMAIR_EL3: return "AMAIR_EL3";
- case VBAR_EL1: return "VBAR_EL1";
- case VBAR_EL2: return "VBAR_EL2";
- case VBAR_EL3: return "VBAR_EL3";
- case RVBAR_EL1: return "RVBAR_EL1";
- case RVBAR_EL2: return "RVBAR_EL2";
- case RVBAR_EL3: return "RVBAR_EL3";
- case ISR_EL1: return "ISR_EL1";
- case CONTEXTIDR_EL1: return "CONTEXTIDR_EL1";
- case TPIDR_EL0: return "TPIDR_EL0";
- case TPIDRRO_EL0: return "TPIDRRO_EL0";
- case TPIDR_EL1: return "TPIDR_EL1";
- case TPIDR_EL2: return "TPIDR_EL2";
- case TPIDR_EL3: return "TPIDR_EL3";
- case TEECR32_EL1: return "TEECR32_EL1";
- case CNTFRQ_EL0: return "CNTFRQ_EL0";
- case CNTPCT_EL0: return "CNTPCT_EL0";
- case CNTVCT_EL0: return "CNTVCT_EL0";
- case CNTVOFF_EL2: return "CNTVOFF_EL2";
- case CNTKCTL_EL1: return "CNTKCTL_EL1";
- case CNTHCTL_EL2: return "CNTHCTL_EL2";
- case CNTP_TVAL_EL0: return "CNTP_TVAL_EL0";
- case CNTP_CTL_EL0: return "CNTP_CTL_EL0";
- case CNTP_CVAL_EL0: return "CNTP_CVAL_EL0";
- case CNTV_TVAL_EL0: return "CNTV_TVAL_EL0";
- case CNTV_CTL_EL0: return "CNTV_CTL_EL0";
- case CNTV_CVAL_EL0: return "CNTV_CVAL_EL0";
- case CNTHP_TVAL_EL2: return "CNTHP_TVAL_EL2";
- case CNTHP_CTL_EL2: return "CNTHP_CTL_EL2";
- case CNTHP_CVAL_EL2: return "CNTHP_CVAL_EL2";
- case CNTPS_TVAL_EL1: return "CNTPS_TVAL_EL1";
- case CNTPS_CTL_EL1: return "CNTPS_CTL_EL1";
- case CNTPS_CVAL_EL1: return "CNTPS_CVAL_EL1";
- case DACR32_EL2: return "DACR32_EL2";
- case IFSR32_EL2: return "IFSR32_EL2";
- case TEEHBR32_EL1: return "TEEHBR32_EL1";
- case SDER32_EL3: return "SDER32_EL3";
- case FPEXC32_EL2: return "FPEXC32_EL2";
- case PMEVCNTR0_EL0: return "PMEVCNTR0_EL0";
- case PMEVCNTR1_EL0: return "PMEVCNTR1_EL0";
- case PMEVCNTR2_EL0: return "PMEVCNTR2_EL0";
- case PMEVCNTR3_EL0: return "PMEVCNTR3_EL0";
- case PMEVCNTR4_EL0: return "PMEVCNTR4_EL0";
- case PMEVCNTR5_EL0: return "PMEVCNTR5_EL0";
- case PMEVCNTR6_EL0: return "PMEVCNTR6_EL0";
- case PMEVCNTR7_EL0: return "PMEVCNTR7_EL0";
- case PMEVCNTR8_EL0: return "PMEVCNTR8_EL0";
- case PMEVCNTR9_EL0: return "PMEVCNTR9_EL0";
- case PMEVCNTR10_EL0: return "PMEVCNTR10_EL0";
- case PMEVCNTR11_EL0: return "PMEVCNTR11_EL0";
- case PMEVCNTR12_EL0: return "PMEVCNTR12_EL0";
- case PMEVCNTR13_EL0: return "PMEVCNTR13_EL0";
- case PMEVCNTR14_EL0: return "PMEVCNTR14_EL0";
- case PMEVCNTR15_EL0: return "PMEVCNTR15_EL0";
- case PMEVCNTR16_EL0: return "PMEVCNTR16_EL0";
- case PMEVCNTR17_EL0: return "PMEVCNTR17_EL0";
- case PMEVCNTR18_EL0: return "PMEVCNTR18_EL0";
- case PMEVCNTR19_EL0: return "PMEVCNTR19_EL0";
- case PMEVCNTR20_EL0: return "PMEVCNTR20_EL0";
- case PMEVCNTR21_EL0: return "PMEVCNTR21_EL0";
- case PMEVCNTR22_EL0: return "PMEVCNTR22_EL0";
- case PMEVCNTR23_EL0: return "PMEVCNTR23_EL0";
- case PMEVCNTR24_EL0: return "PMEVCNTR24_EL0";
- case PMEVCNTR25_EL0: return "PMEVCNTR25_EL0";
- case PMEVCNTR26_EL0: return "PMEVCNTR26_EL0";
- case PMEVCNTR27_EL0: return "PMEVCNTR27_EL0";
- case PMEVCNTR28_EL0: return "PMEVCNTR28_EL0";
- case PMEVCNTR29_EL0: return "PMEVCNTR29_EL0";
- case PMEVCNTR30_EL0: return "PMEVCNTR30_EL0";
- case PMEVTYPER0_EL0: return "PMEVTYPER0_EL0";
- case PMEVTYPER1_EL0: return "PMEVTYPER1_EL0";
- case PMEVTYPER2_EL0: return "PMEVTYPER2_EL0";
- case PMEVTYPER3_EL0: return "PMEVTYPER3_EL0";
- case PMEVTYPER4_EL0: return "PMEVTYPER4_EL0";
- case PMEVTYPER5_EL0: return "PMEVTYPER5_EL0";
- case PMEVTYPER6_EL0: return "PMEVTYPER6_EL0";
- case PMEVTYPER7_EL0: return "PMEVTYPER7_EL0";
- case PMEVTYPER8_EL0: return "PMEVTYPER8_EL0";
- case PMEVTYPER9_EL0: return "PMEVTYPER9_EL0";
- case PMEVTYPER10_EL0: return "PMEVTYPER10_EL0";
- case PMEVTYPER11_EL0: return "PMEVTYPER11_EL0";
- case PMEVTYPER12_EL0: return "PMEVTYPER12_EL0";
- case PMEVTYPER13_EL0: return "PMEVTYPER13_EL0";
- case PMEVTYPER14_EL0: return "PMEVTYPER14_EL0";
- case PMEVTYPER15_EL0: return "PMEVTYPER15_EL0";
- case PMEVTYPER16_EL0: return "PMEVTYPER16_EL0";
- case PMEVTYPER17_EL0: return "PMEVTYPER17_EL0";
- case PMEVTYPER18_EL0: return "PMEVTYPER18_EL0";
- case PMEVTYPER19_EL0: return "PMEVTYPER19_EL0";
- case PMEVTYPER20_EL0: return "PMEVTYPER20_EL0";
- case PMEVTYPER21_EL0: return "PMEVTYPER21_EL0";
- case PMEVTYPER22_EL0: return "PMEVTYPER22_EL0";
- case PMEVTYPER23_EL0: return "PMEVTYPER23_EL0";
- case PMEVTYPER24_EL0: return "PMEVTYPER24_EL0";
- case PMEVTYPER25_EL0: return "PMEVTYPER25_EL0";
- case PMEVTYPER26_EL0: return "PMEVTYPER26_EL0";
- case PMEVTYPER27_EL0: return "PMEVTYPER27_EL0";
- case PMEVTYPER28_EL0: return "PMEVTYPER28_EL0";
- case PMEVTYPER29_EL0: return "PMEVTYPER29_EL0";
- case PMEVTYPER30_EL0: return "PMEVTYPER30_EL0";
- case PMCCFILTR_EL0: return "PMCCFILTR_EL0";
- case RMR_EL3: return "RMR_EL3";
- case RMR_EL2: return "RMR_EL2";
- case RMR_EL1: return "RMR_EL1";
- case CPM_IOACC_CTL_EL3: return "CPM_IOACC_CTL_EL3";
- case MDCCSR_EL0: return "MDCCSR_EL0";
- case MDCCINT_EL1: return "MDCCINT_EL1";
- case DBGDTR_EL0: return "DBGDTR_EL0";
- case DBGDTRRX_EL0: return "DBGDTRRX_EL0";
- case DBGVCR32_EL2: return "DBGVCR32_EL2";
- case OSDTRRX_EL1: return "OSDTRRX_EL1";
- case MDSCR_EL1: return "MDSCR_EL1";
- case OSDTRTX_EL1: return "OSDTRTX_EL1";
- case OSECCR_EL11: return "OSECCR_EL11";
- case DBGBVR0_EL1: return "DBGBVR0_EL1";
- case DBGBVR1_EL1: return "DBGBVR1_EL1";
- case DBGBVR2_EL1: return "DBGBVR2_EL1";
- case DBGBVR3_EL1: return "DBGBVR3_EL1";
- case DBGBVR4_EL1: return "DBGBVR4_EL1";
- case DBGBVR5_EL1: return "DBGBVR5_EL1";
- case DBGBVR6_EL1: return "DBGBVR6_EL1";
- case DBGBVR7_EL1: return "DBGBVR7_EL1";
- case DBGBVR8_EL1: return "DBGBVR8_EL1";
- case DBGBVR9_EL1: return "DBGBVR9_EL1";
- case DBGBVR10_EL1: return "DBGBVR10_EL1";
- case DBGBVR11_EL1: return "DBGBVR11_EL1";
- case DBGBVR12_EL1: return "DBGBVR12_EL1";
- case DBGBVR13_EL1: return "DBGBVR13_EL1";
- case DBGBVR14_EL1: return "DBGBVR14_EL1";
- case DBGBVR15_EL1: return "DBGBVR15_EL1";
- case DBGBCR0_EL1: return "DBGBCR0_EL1";
- case DBGBCR1_EL1: return "DBGBCR1_EL1";
- case DBGBCR2_EL1: return "DBGBCR2_EL1";
- case DBGBCR3_EL1: return "DBGBCR3_EL1";
- case DBGBCR4_EL1: return "DBGBCR4_EL1";
- case DBGBCR5_EL1: return "DBGBCR5_EL1";
- case DBGBCR6_EL1: return "DBGBCR6_EL1";
- case DBGBCR7_EL1: return "DBGBCR7_EL1";
- case DBGBCR8_EL1: return "DBGBCR8_EL1";
- case DBGBCR9_EL1: return "DBGBCR9_EL1";
- case DBGBCR10_EL1: return "DBGBCR10_EL1";
- case DBGBCR11_EL1: return "DBGBCR11_EL1";
- case DBGBCR12_EL1: return "DBGBCR12_EL1";
- case DBGBCR13_EL1: return "DBGBCR13_EL1";
- case DBGBCR14_EL1: return "DBGBCR14_EL1";
- case DBGBCR15_EL1: return "DBGBCR15_EL1";
- case DBGWVR0_EL1: return "DBGWVR0_EL1";
- case DBGWVR1_EL1: return "DBGWVR1_EL1";
- case DBGWVR2_EL1: return "DBGWVR2_EL1";
- case DBGWVR3_EL1: return "DBGWVR3_EL1";
- case DBGWVR4_EL1: return "DBGWVR4_EL1";
- case DBGWVR5_EL1: return "DBGWVR5_EL1";
- case DBGWVR6_EL1: return "DBGWVR6_EL1";
- case DBGWVR7_EL1: return "DBGWVR7_EL1";
- case DBGWVR8_EL1: return "DBGWVR8_EL1";
- case DBGWVR9_EL1: return "DBGWVR9_EL1";
- case DBGWVR10_EL1: return "DBGWVR10_EL1";
- case DBGWVR11_EL1: return "DBGWVR11_EL1";
- case DBGWVR12_EL1: return "DBGWVR12_EL1";
- case DBGWVR13_EL1: return "DBGWVR13_EL1";
- case DBGWVR14_EL1: return "DBGWVR14_EL1";
- case DBGWVR15_EL1: return "DBGWVR15_EL1";
- case DBGWCR0_EL1: return "DBGWCR0_EL1";
- case DBGWCR1_EL1: return "DBGWCR1_EL1";
- case DBGWCR2_EL1: return "DBGWCR2_EL1";
- case DBGWCR3_EL1: return "DBGWCR3_EL1";
- case DBGWCR4_EL1: return "DBGWCR4_EL1";
- case DBGWCR5_EL1: return "DBGWCR5_EL1";
- case DBGWCR6_EL1: return "DBGWCR6_EL1";
- case DBGWCR7_EL1: return "DBGWCR7_EL1";
- case DBGWCR8_EL1: return "DBGWCR8_EL1";
- case DBGWCR9_EL1: return "DBGWCR9_EL1";
- case DBGWCR10_EL1: return "DBGWCR10_EL1";
- case DBGWCR11_EL1: return "DBGWCR11_EL1";
- case DBGWCR12_EL1: return "DBGWCR12_EL1";
- case DBGWCR13_EL1: return "DBGWCR13_EL1";
- case DBGWCR14_EL1: return "DBGWCR14_EL1";
- case DBGWCR15_EL1: return "DBGWCR15_EL1";
- case MDRAR_EL1: return "MDRAR_EL1";
- case OSLAR_EL1: return "OSLAR_EL1";
- case OSLSR_EL1: return "OSLSR_EL1";
- case OSDLR_EL1: return "OSDLR_EL1";
- case DBGPRCR_EL1: return "DBGPRCR_EL1";
- case DBGCLAIMSET_EL1: return "DBGCLAIMSET_EL1";
- case DBGCLAIMCLR_EL1: return "DBGCLAIMCLR_EL1";
- case DBGAUTHSTATUS_EL1: return "DBGAUTHSTATUS_EL1";
- case DBGDEVID2: return "DBGDEVID2";
- case DBGDEVID1: return "DBGDEVID1";
- case DBGDEVID0: return "DBGDEVID0";
- case ID_PFR0_EL1: return "ID_PFR0_EL1";
- case ID_PFR1_EL1: return "ID_PFR1_EL1";
- case ID_DFR0_EL1: return "ID_DFR0_EL1";
- case ID_AFR0_EL1: return "ID_AFR0_EL1";
- case ID_ISAR0_EL1: return "ID_ISAR0_EL1";
- case ID_ISAR1_EL1: return "ID_ISAR1_EL1";
- case ID_ISAR2_EL1: return "ID_ISAR2_EL1";
- case ID_ISAR3_EL1: return "ID_ISAR3_EL1";
- case ID_ISAR4_EL1: return "ID_ISAR4_EL1";
- case ID_ISAR5_EL1: return "ID_ISAR5_EL1";
- case AFSR1_EL1: return "AFSR1_EL1";
- case AFSR0_EL1: return "AFSR0_EL1";
- case REVIDR_EL1: return "REVIDR_EL1";
- }
-}
-
-enum CPSRField {
- InvalidCPSRField = 0xff,
- cpsr_SPSel = 0x5,
- cpsr_DAIFSet = 0x1e,
- cpsr_DAIFClr = 0x1f
-};
-
-static inline const char *getCPSRFieldName(CPSRField Val) {
- switch(Val) {
- default: assert(0 && "Invalid system register value!");
- case cpsr_SPSel: return "SPSel";
- case cpsr_DAIFSet: return "DAIFSet";
- case cpsr_DAIFClr: return "DAIFClr";
- }
-}
-
-} // end namespace ARM64SYS
-
-namespace ARM64II {
- /// Target Operand Flag enum.
- enum TOF {
- //===------------------------------------------------------------------===//
- // ARM64 Specific MachineOperand flags.
-
- MO_NO_FLAG,
-
- MO_FRAGMENT = 0x7,
-
- /// MO_PAGE - A symbol operand with this flag represents the pc-relative
- /// offset of the 4K page containing the symbol. This is used with the
- /// ADRP instruction.
- MO_PAGE = 1,
-
- /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
- /// that symbol within a 4K page. This offset is added to the page address
- /// to produce the complete address.
- MO_PAGEOFF = 2,
-
- /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
- /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
- MO_G3 = 3,
-
- /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
- /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
- MO_G2 = 4,
-
- /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
- /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
- MO_G1 = 5,
-
- /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
- /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
- MO_G0 = 6,
-
- /// MO_GOT - This flag indicates that a symbol operand represents the
- /// address of the GOT entry for the symbol, rather than the address of
- /// the symbol itself.
- MO_GOT = 8,
-
- /// MO_NC - Indicates whether the linker is expected to check the symbol
- /// reference for overflow. For example in an ADRP/ADD pair of relocations
- /// the ADRP usually does check, but not the ADD.
- MO_NC = 0x10,
-
- /// MO_TLS - Indicates that the operand being accessed is some kind of
- /// thread-local symbol. On Darwin, only one type of thread-local access
- /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
- /// referee will affect interpretation.
- MO_TLS = 0x20
- };
-} // end namespace ARM64II
-
-} // end namespace llvm
-
-#endif
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
index 19559f8..95020e4 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
@@ -13,9 +13,9 @@
#define DEBUG_TYPE "mccodeemitter"
#include "MCTargetDesc/ARM64AddressingModes.h"
-#include "MCTargetDesc/ARM64BaseInfo.h"
#include "MCTargetDesc/ARM64FixupKinds.h"
#include "MCTargetDesc/ARM64MCExpr.h"
+#include "Utils/ARM64BaseInfo.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInst.h"
@@ -176,6 +176,16 @@ public:
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+
+ unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
+ const MCSubtargetInfo &STI) const;
+
+ template<int hasRs, int hasRt2> unsigned
+ fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
+ const MCSubtargetInfo &STI) const;
+
+ unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
+ const MCSubtargetInfo &STI) const;
};
} // end anonymous namespace
@@ -560,4 +570,34 @@ void ARM64MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
++MCNumEmitted; // Keep track of the # of mi's emitted.
}
+unsigned
+ARM64MCCodeEmitter::fixMulHigh(const MCInst &MI,
+ unsigned EncodedValue,
+ const MCSubtargetInfo &STI) const {
+ // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
+ // (i.e. all bits 1) but is ignored by the processor.
+ EncodedValue |= 0x1f << 10;
+ return EncodedValue;
+}
+
+template<int hasRs, int hasRt2> unsigned
+ARM64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
+ unsigned EncodedValue,
+ const MCSubtargetInfo &STI) const {
+ if (!hasRs) EncodedValue |= 0x001F0000;
+ if (!hasRt2) EncodedValue |= 0x00007C00;
+
+ return EncodedValue;
+}
+
+unsigned
+ARM64MCCodeEmitter::fixOneOperandFPComparison(const MCInst &MI,
+ unsigned EncodedValue,
+ const MCSubtargetInfo &STI) const {
+ // The Rm field of FCMP and friends is unused - it should be assembled
+ // as 0, but is ignored by the processor.
+ EncodedValue &= ~(0x1f << 16);
+ return EncodedValue;
+}
+
#include "ARM64GenMCCodeEmitter.inc"
diff --git a/lib/Target/ARM64/Makefile b/lib/Target/ARM64/Makefile
index 5f0f307..cfb05d2 100644
--- a/lib/Target/ARM64/Makefile
+++ b/lib/Target/ARM64/Makefile
@@ -20,6 +20,6 @@ BUILT_SOURCES = ARM64GenRegisterInfo.inc ARM64GenInstrInfo.inc \
ARM64GenFastISel.inc ARM64GenDisassemblerTables.inc \
ARM64GenMCPseudoLowering.inc
-DIRS = TargetInfo InstPrinter AsmParser Disassembler MCTargetDesc
+DIRS = TargetInfo InstPrinter AsmParser Disassembler MCTargetDesc Utils
include $(LEVEL)/Makefile.common
diff --git a/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp b/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp
new file mode 100644
index 0000000..8ab18e5
--- /dev/null
+++ b/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp
@@ -0,0 +1,871 @@
+//===-- ARM64BaseInfo.cpp - ARM64 Base encoding information------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for ARM64.
+//
+//===----------------------------------------------------------------------===//
+#include "ARM64BaseInfo.h"
+#include "llvm/ADT/APFloat.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/Support/Regex.h"
+
+using namespace llvm;
+
+StringRef ARM64NamedImmMapper::toString(uint32_t Value, bool &Valid) const {
+ for (unsigned i = 0; i < NumPairs; ++i) {
+ if (Pairs[i].Value == Value) {
+ Valid = true;
+ return Pairs[i].Name;
+ }
+ }
+
+ Valid = false;
+ return StringRef();
+}
+
+uint32_t ARM64NamedImmMapper::fromString(StringRef Name, bool &Valid) const {
+ std::string LowerCaseName = Name.lower();
+ for (unsigned i = 0; i < NumPairs; ++i) {
+ if (Pairs[i].Name == LowerCaseName) {
+ Valid = true;
+ return Pairs[i].Value;
+ }
+ }
+
+ Valid = false;
+ return -1;
+}
+
+bool ARM64NamedImmMapper::validImm(uint32_t Value) const {
+ return Value < TooBigImm;
+}
+
+const ARM64NamedImmMapper::Mapping ARM64AT::ATMapper::ATPairs[] = {
+ {"s1e1r", S1E1R},
+ {"s1e2r", S1E2R},
+ {"s1e3r", S1E3R},
+ {"s1e1w", S1E1W},
+ {"s1e2w", S1E2W},
+ {"s1e3w", S1E3W},
+ {"s1e0r", S1E0R},
+ {"s1e0w", S1E0W},
+ {"s12e1r", S12E1R},
+ {"s12e1w", S12E1W},
+ {"s12e0r", S12E0R},
+ {"s12e0w", S12E0W},
+};
+
+ARM64AT::ATMapper::ATMapper()
+ : ARM64NamedImmMapper(ATPairs, 0) {}
+
+const ARM64NamedImmMapper::Mapping ARM64DB::DBarrierMapper::DBarrierPairs[] = {
+ {"oshld", OSHLD},
+ {"oshst", OSHST},
+ {"osh", OSH},
+ {"nshld", NSHLD},
+ {"nshst", NSHST},
+ {"nsh", NSH},
+ {"ishld", ISHLD},
+ {"ishst", ISHST},
+ {"ish", ISH},
+ {"ld", LD},
+ {"st", ST},
+ {"sy", SY}
+};
+
+ARM64DB::DBarrierMapper::DBarrierMapper()
+ : ARM64NamedImmMapper(DBarrierPairs, 16u) {}
+
+const ARM64NamedImmMapper::Mapping ARM64DC::DCMapper::DCPairs[] = {
+ {"zva", ZVA},
+ {"ivac", IVAC},
+ {"isw", ISW},
+ {"cvac", CVAC},
+ {"csw", CSW},
+ {"cvau", CVAU},
+ {"civac", CIVAC},
+ {"cisw", CISW}
+};
+
+ARM64DC::DCMapper::DCMapper()
+ : ARM64NamedImmMapper(DCPairs, 0) {}
+
+const ARM64NamedImmMapper::Mapping ARM64IC::ICMapper::ICPairs[] = {
+ {"ialluis", IALLUIS},
+ {"iallu", IALLU},
+ {"ivau", IVAU}
+};
+
+ARM64IC::ICMapper::ICMapper()
+ : ARM64NamedImmMapper(ICPairs, 0) {}
+
+const ARM64NamedImmMapper::Mapping ARM64ISB::ISBMapper::ISBPairs[] = {
+ {"sy", SY},
+};
+
+ARM64ISB::ISBMapper::ISBMapper()
+ : ARM64NamedImmMapper(ISBPairs, 16) {}
+
+const ARM64NamedImmMapper::Mapping ARM64PRFM::PRFMMapper::PRFMPairs[] = {
+ {"pldl1keep", PLDL1KEEP},
+ {"pldl1strm", PLDL1STRM},
+ {"pldl2keep", PLDL2KEEP},
+ {"pldl2strm", PLDL2STRM},
+ {"pldl3keep", PLDL3KEEP},
+ {"pldl3strm", PLDL3STRM},
+ {"plil1keep", PLIL1KEEP},
+ {"plil1strm", PLIL1STRM},
+ {"plil2keep", PLIL2KEEP},
+ {"plil2strm", PLIL2STRM},
+ {"plil3keep", PLIL3KEEP},
+ {"plil3strm", PLIL3STRM},
+ {"pstl1keep", PSTL1KEEP},
+ {"pstl1strm", PSTL1STRM},
+ {"pstl2keep", PSTL2KEEP},
+ {"pstl2strm", PSTL2STRM},
+ {"pstl3keep", PSTL3KEEP},
+ {"pstl3strm", PSTL3STRM}
+};
+
+ARM64PRFM::PRFMMapper::PRFMMapper()
+ : ARM64NamedImmMapper(PRFMPairs, 32) {}
+
+const ARM64NamedImmMapper::Mapping ARM64PState::PStateMapper::PStatePairs[] = {
+ {"spsel", SPSel},
+ {"daifset", DAIFSet},
+ {"daifclr", DAIFClr}
+};
+
+ARM64PState::PStateMapper::PStateMapper()
+ : ARM64NamedImmMapper(PStatePairs, 0) {}
+
+const ARM64NamedImmMapper::Mapping ARM64SysReg::MRSMapper::MRSPairs[] = {
+ {"mdccsr_el0", MDCCSR_EL0},
+ {"dbgdtrrx_el0", DBGDTRRX_EL0},
+ {"mdrar_el1", MDRAR_EL1},
+ {"oslsr_el1", OSLSR_EL1},
+ {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1},
+ {"pmceid0_el0", PMCEID0_EL0},
+ {"pmceid1_el0", PMCEID1_EL0},
+ {"midr_el1", MIDR_EL1},
+ {"ccsidr_el1", CCSIDR_EL1},
+ {"clidr_el1", CLIDR_EL1},
+ {"ctr_el0", CTR_EL0},
+ {"mpidr_el1", MPIDR_EL1},
+ {"revidr_el1", REVIDR_EL1},
+ {"aidr_el1", AIDR_EL1},
+ {"dczid_el0", DCZID_EL0},
+ {"id_pfr0_el1", ID_PFR0_EL1},
+ {"id_pfr1_el1", ID_PFR1_EL1},
+ {"id_dfr0_el1", ID_DFR0_EL1},
+ {"id_afr0_el1", ID_AFR0_EL1},
+ {"id_mmfr0_el1", ID_MMFR0_EL1},
+ {"id_mmfr1_el1", ID_MMFR1_EL1},
+ {"id_mmfr2_el1", ID_MMFR2_EL1},
+ {"id_mmfr3_el1", ID_MMFR3_EL1},
+ {"id_isar0_el1", ID_ISAR0_EL1},
+ {"id_isar1_el1", ID_ISAR1_EL1},
+ {"id_isar2_el1", ID_ISAR2_EL1},
+ {"id_isar3_el1", ID_ISAR3_EL1},
+ {"id_isar4_el1", ID_ISAR4_EL1},
+ {"id_isar5_el1", ID_ISAR5_EL1},
+ {"id_aa64pfr0_el1", ID_AARM64PFR0_EL1},
+ {"id_aa64pfr1_el1", ID_AARM64PFR1_EL1},
+ {"id_aa64dfr0_el1", ID_AARM64DFR0_EL1},
+ {"id_aa64dfr1_el1", ID_AARM64DFR1_EL1},
+ {"id_aa64afr0_el1", ID_AARM64AFR0_EL1},
+ {"id_aa64afr1_el1", ID_AARM64AFR1_EL1},
+ {"id_aa64isar0_el1", ID_AARM64ISAR0_EL1},
+ {"id_aa64isar1_el1", ID_AARM64ISAR1_EL1},
+ {"id_aa64mmfr0_el1", ID_AARM64MMFR0_EL1},
+ {"id_aa64mmfr1_el1", ID_AARM64MMFR1_EL1},
+ {"mvfr0_el1", MVFR0_EL1},
+ {"mvfr1_el1", MVFR1_EL1},
+ {"mvfr2_el1", MVFR2_EL1},
+ {"rvbar_el1", RVBAR_EL1},
+ {"rvbar_el2", RVBAR_EL2},
+ {"rvbar_el3", RVBAR_EL3},
+ {"isr_el1", ISR_EL1},
+ {"cntpct_el0", CNTPCT_EL0},
+ {"cntvct_el0", CNTVCT_EL0},
+
+ // Trace registers
+ {"trcstatr", TRCSTATR},
+ {"trcidr8", TRCIDR8},
+ {"trcidr9", TRCIDR9},
+ {"trcidr10", TRCIDR10},
+ {"trcidr11", TRCIDR11},
+ {"trcidr12", TRCIDR12},
+ {"trcidr13", TRCIDR13},
+ {"trcidr0", TRCIDR0},
+ {"trcidr1", TRCIDR1},
+ {"trcidr2", TRCIDR2},
+ {"trcidr3", TRCIDR3},
+ {"trcidr4", TRCIDR4},
+ {"trcidr5", TRCIDR5},
+ {"trcidr6", TRCIDR6},
+ {"trcidr7", TRCIDR7},
+ {"trcoslsr", TRCOSLSR},
+ {"trcpdsr", TRCPDSR},
+ {"trcdevaff0", TRCDEVAFF0},
+ {"trcdevaff1", TRCDEVAFF1},
+ {"trclsr", TRCLSR},
+ {"trcauthstatus", TRCAUTHSTATUS},
+ {"trcdevarch", TRCDEVARCH},
+ {"trcdevid", TRCDEVID},
+ {"trcdevtype", TRCDEVTYPE},
+ {"trcpidr4", TRCPIDR4},
+ {"trcpidr5", TRCPIDR5},
+ {"trcpidr6", TRCPIDR6},
+ {"trcpidr7", TRCPIDR7},
+ {"trcpidr0", TRCPIDR0},
+ {"trcpidr1", TRCPIDR1},
+ {"trcpidr2", TRCPIDR2},
+ {"trcpidr3", TRCPIDR3},
+ {"trccidr0", TRCCIDR0},
+ {"trccidr1", TRCCIDR1},
+ {"trccidr2", TRCCIDR2},
+ {"trccidr3", TRCCIDR3},
+
+ // GICv3 registers
+ {"icc_iar1_el1", ICC_IAR1_EL1},
+ {"icc_iar0_el1", ICC_IAR0_EL1},
+ {"icc_hppir1_el1", ICC_HPPIR1_EL1},
+ {"icc_hppir0_el1", ICC_HPPIR0_EL1},
+ {"icc_rpr_el1", ICC_RPR_EL1},
+ {"ich_vtr_el2", ICH_VTR_EL2},
+ {"ich_eisr_el2", ICH_EISR_EL2},
+ {"ich_elsr_el2", ICH_ELSR_EL2}
+};
+
+ARM64SysReg::MRSMapper::MRSMapper() {
+ InstPairs = &MRSPairs[0];
+ NumInstPairs = llvm::array_lengthof(MRSPairs);
+}
+
+const ARM64NamedImmMapper::Mapping ARM64SysReg::MSRMapper::MSRPairs[] = {
+ {"dbgdtrtx_el0", DBGDTRTX_EL0},
+ {"oslar_el1", OSLAR_EL1},
+ {"pmswinc_el0", PMSWINC_EL0},
+
+ // Trace registers
+ {"trcoslar", TRCOSLAR},
+ {"trclar", TRCLAR},
+
+ // GICv3 registers
+ {"icc_eoir1_el1", ICC_EOIR1_EL1},
+ {"icc_eoir0_el1", ICC_EOIR0_EL1},
+ {"icc_dir_el1", ICC_DIR_EL1},
+ {"icc_sgi1r_el1", ICC_SGI1R_EL1},
+ {"icc_asgi1r_el1", ICC_ASGI1R_EL1},
+ {"icc_sgi0r_el1", ICC_SGI0R_EL1}
+};
+
+ARM64SysReg::MSRMapper::MSRMapper() {
+ InstPairs = &MSRPairs[0];
+ NumInstPairs = llvm::array_lengthof(MSRPairs);
+}
+
+
+const ARM64NamedImmMapper::Mapping ARM64SysReg::SysRegMapper::SysRegPairs[] = {
+ {"osdtrrx_el1", OSDTRRX_EL1},
+ {"osdtrtx_el1", OSDTRTX_EL1},
+ {"teecr32_el1", TEECR32_EL1},
+ {"mdccint_el1", MDCCINT_EL1},
+ {"mdscr_el1", MDSCR_EL1},
+ {"dbgdtr_el0", DBGDTR_EL0},
+ {"oseccr_el1", OSECCR_EL1},
+ {"dbgvcr32_el2", DBGVCR32_EL2},
+ {"dbgbvr0_el1", DBGBVR0_EL1},
+ {"dbgbvr1_el1", DBGBVR1_EL1},
+ {"dbgbvr2_el1", DBGBVR2_EL1},
+ {"dbgbvr3_el1", DBGBVR3_EL1},
+ {"dbgbvr4_el1", DBGBVR4_EL1},
+ {"dbgbvr5_el1", DBGBVR5_EL1},
+ {"dbgbvr6_el1", DBGBVR6_EL1},
+ {"dbgbvr7_el1", DBGBVR7_EL1},
+ {"dbgbvr8_el1", DBGBVR8_EL1},
+ {"dbgbvr9_el1", DBGBVR9_EL1},
+ {"dbgbvr10_el1", DBGBVR10_EL1},
+ {"dbgbvr11_el1", DBGBVR11_EL1},
+ {"dbgbvr12_el1", DBGBVR12_EL1},
+ {"dbgbvr13_el1", DBGBVR13_EL1},
+ {"dbgbvr14_el1", DBGBVR14_EL1},
+ {"dbgbvr15_el1", DBGBVR15_EL1},
+ {"dbgbcr0_el1", DBGBCR0_EL1},
+ {"dbgbcr1_el1", DBGBCR1_EL1},
+ {"dbgbcr2_el1", DBGBCR2_EL1},
+ {"dbgbcr3_el1", DBGBCR3_EL1},
+ {"dbgbcr4_el1", DBGBCR4_EL1},
+ {"dbgbcr5_el1", DBGBCR5_EL1},
+ {"dbgbcr6_el1", DBGBCR6_EL1},
+ {"dbgbcr7_el1", DBGBCR7_EL1},
+ {"dbgbcr8_el1", DBGBCR8_EL1},
+ {"dbgbcr9_el1", DBGBCR9_EL1},
+ {"dbgbcr10_el1", DBGBCR10_EL1},
+ {"dbgbcr11_el1", DBGBCR11_EL1},
+ {"dbgbcr12_el1", DBGBCR12_EL1},
+ {"dbgbcr13_el1", DBGBCR13_EL1},
+ {"dbgbcr14_el1", DBGBCR14_EL1},
+ {"dbgbcr15_el1", DBGBCR15_EL1},
+ {"dbgwvr0_el1", DBGWVR0_EL1},
+ {"dbgwvr1_el1", DBGWVR1_EL1},
+ {"dbgwvr2_el1", DBGWVR2_EL1},
+ {"dbgwvr3_el1", DBGWVR3_EL1},
+ {"dbgwvr4_el1", DBGWVR4_EL1},
+ {"dbgwvr5_el1", DBGWVR5_EL1},
+ {"dbgwvr6_el1", DBGWVR6_EL1},
+ {"dbgwvr7_el1", DBGWVR7_EL1},
+ {"dbgwvr8_el1", DBGWVR8_EL1},
+ {"dbgwvr9_el1", DBGWVR9_EL1},
+ {"dbgwvr10_el1", DBGWVR10_EL1},
+ {"dbgwvr11_el1", DBGWVR11_EL1},
+ {"dbgwvr12_el1", DBGWVR12_EL1},
+ {"dbgwvr13_el1", DBGWVR13_EL1},
+ {"dbgwvr14_el1", DBGWVR14_EL1},
+ {"dbgwvr15_el1", DBGWVR15_EL1},
+ {"dbgwcr0_el1", DBGWCR0_EL1},
+ {"dbgwcr1_el1", DBGWCR1_EL1},
+ {"dbgwcr2_el1", DBGWCR2_EL1},
+ {"dbgwcr3_el1", DBGWCR3_EL1},
+ {"dbgwcr4_el1", DBGWCR4_EL1},
+ {"dbgwcr5_el1", DBGWCR5_EL1},
+ {"dbgwcr6_el1", DBGWCR6_EL1},
+ {"dbgwcr7_el1", DBGWCR7_EL1},
+ {"dbgwcr8_el1", DBGWCR8_EL1},
+ {"dbgwcr9_el1", DBGWCR9_EL1},
+ {"dbgwcr10_el1", DBGWCR10_EL1},
+ {"dbgwcr11_el1", DBGWCR11_EL1},
+ {"dbgwcr12_el1", DBGWCR12_EL1},
+ {"dbgwcr13_el1", DBGWCR13_EL1},
+ {"dbgwcr14_el1", DBGWCR14_EL1},
+ {"dbgwcr15_el1", DBGWCR15_EL1},
+ {"teehbr32_el1", TEEHBR32_EL1},
+ {"osdlr_el1", OSDLR_EL1},
+ {"dbgprcr_el1", DBGPRCR_EL1},
+ {"dbgclaimset_el1", DBGCLAIMSET_EL1},
+ {"dbgclaimclr_el1", DBGCLAIMCLR_EL1},
+ {"csselr_el1", CSSELR_EL1},
+ {"vpidr_el2", VPIDR_EL2},
+ {"vmpidr_el2", VMPIDR_EL2},
+ {"sctlr_el1", SCTLR_EL1},
+ {"sctlr_el2", SCTLR_EL2},
+ {"sctlr_el3", SCTLR_EL3},
+ {"actlr_el1", ACTLR_EL1},
+ {"actlr_el2", ACTLR_EL2},
+ {"actlr_el3", ACTLR_EL3},
+ {"cpacr_el1", CPACR_EL1},
+ {"hcr_el2", HCR_EL2},
+ {"scr_el3", SCR_EL3},
+ {"mdcr_el2", MDCR_EL2},
+ {"sder32_el3", SDER32_EL3},
+ {"cptr_el2", CPTR_EL2},
+ {"cptr_el3", CPTR_EL3},
+ {"hstr_el2", HSTR_EL2},
+ {"hacr_el2", HACR_EL2},
+ {"mdcr_el3", MDCR_EL3},
+ {"ttbr0_el1", TTBR0_EL1},
+ {"ttbr0_el2", TTBR0_EL2},
+ {"ttbr0_el3", TTBR0_EL3},
+ {"ttbr1_el1", TTBR1_EL1},
+ {"tcr_el1", TCR_EL1},
+ {"tcr_el2", TCR_EL2},
+ {"tcr_el3", TCR_EL3},
+ {"vttbr_el2", VTTBR_EL2},
+ {"vtcr_el2", VTCR_EL2},
+ {"dacr32_el2", DACR32_EL2},
+ {"spsr_el1", SPSR_EL1},
+ {"spsr_el2", SPSR_EL2},
+ {"spsr_el3", SPSR_EL3},
+ {"elr_el1", ELR_EL1},
+ {"elr_el2", ELR_EL2},
+ {"elr_el3", ELR_EL3},
+ {"sp_el0", SP_EL0},
+ {"sp_el1", SP_EL1},
+ {"sp_el2", SP_EL2},
+ {"spsel", SPSel},
+ {"nzcv", NZCV},
+ {"daif", DAIF},
+ {"currentel", CurrentEL},
+ {"spsr_irq", SPSR_irq},
+ {"spsr_abt", SPSR_abt},
+ {"spsr_und", SPSR_und},
+ {"spsr_fiq", SPSR_fiq},
+ {"fpcr", FPCR},
+ {"fpsr", FPSR},
+ {"dspsr_el0", DSPSR_EL0},
+ {"dlr_el0", DLR_EL0},
+ {"ifsr32_el2", IFSR32_EL2},
+ {"afsr0_el1", AFSR0_EL1},
+ {"afsr0_el2", AFSR0_EL2},
+ {"afsr0_el3", AFSR0_EL3},
+ {"afsr1_el1", AFSR1_EL1},
+ {"afsr1_el2", AFSR1_EL2},
+ {"afsr1_el3", AFSR1_EL3},
+ {"esr_el1", ESR_EL1},
+ {"esr_el2", ESR_EL2},
+ {"esr_el3", ESR_EL3},
+ {"fpexc32_el2", FPEXC32_EL2},
+ {"far_el1", FAR_EL1},
+ {"far_el2", FAR_EL2},
+ {"far_el3", FAR_EL3},
+ {"hpfar_el2", HPFAR_EL2},
+ {"par_el1", PAR_EL1},
+ {"pmcr_el0", PMCR_EL0},
+ {"pmcntenset_el0", PMCNTENSET_EL0},
+ {"pmcntenclr_el0", PMCNTENCLR_EL0},
+ {"pmovsclr_el0", PMOVSCLR_EL0},
+ {"pmselr_el0", PMSELR_EL0},
+ {"pmccntr_el0", PMCCNTR_EL0},
+ {"pmxevtyper_el0", PMXEVTYPER_EL0},
+ {"pmxevcntr_el0", PMXEVCNTR_EL0},
+ {"pmuserenr_el0", PMUSERENR_EL0},
+ {"pmintenset_el1", PMINTENSET_EL1},
+ {"pmintenclr_el1", PMINTENCLR_EL1},
+ {"pmovsset_el0", PMOVSSET_EL0},
+ {"mair_el1", MAIR_EL1},
+ {"mair_el2", MAIR_EL2},
+ {"mair_el3", MAIR_EL3},
+ {"amair_el1", AMAIR_EL1},
+ {"amair_el2", AMAIR_EL2},
+ {"amair_el3", AMAIR_EL3},
+ {"vbar_el1", VBAR_EL1},
+ {"vbar_el2", VBAR_EL2},
+ {"vbar_el3", VBAR_EL3},
+ {"rmr_el1", RMR_EL1},
+ {"rmr_el2", RMR_EL2},
+ {"rmr_el3", RMR_EL3},
+ {"contextidr_el1", CONTEXTIDR_EL1},
+ {"tpidr_el0", TPIDR_EL0},
+ {"tpidr_el2", TPIDR_EL2},
+ {"tpidr_el3", TPIDR_EL3},
+ {"tpidrro_el0", TPIDRRO_EL0},
+ {"tpidr_el1", TPIDR_EL1},
+ {"cntfrq_el0", CNTFRQ_EL0},
+ {"cntvoff_el2", CNTVOFF_EL2},
+ {"cntkctl_el1", CNTKCTL_EL1},
+ {"cnthctl_el2", CNTHCTL_EL2},
+ {"cntp_tval_el0", CNTP_TVAL_EL0},
+ {"cnthp_tval_el2", CNTHP_TVAL_EL2},
+ {"cntps_tval_el1", CNTPS_TVAL_EL1},
+ {"cntp_ctl_el0", CNTP_CTL_EL0},
+ {"cnthp_ctl_el2", CNTHP_CTL_EL2},
+ {"cntps_ctl_el1", CNTPS_CTL_EL1},
+ {"cntp_cval_el0", CNTP_CVAL_EL0},
+ {"cnthp_cval_el2", CNTHP_CVAL_EL2},
+ {"cntps_cval_el1", CNTPS_CVAL_EL1},
+ {"cntv_tval_el0", CNTV_TVAL_EL0},
+ {"cntv_ctl_el0", CNTV_CTL_EL0},
+ {"cntv_cval_el0", CNTV_CVAL_EL0},
+ {"pmevcntr0_el0", PMEVCNTR0_EL0},
+ {"pmevcntr1_el0", PMEVCNTR1_EL0},
+ {"pmevcntr2_el0", PMEVCNTR2_EL0},
+ {"pmevcntr3_el0", PMEVCNTR3_EL0},
+ {"pmevcntr4_el0", PMEVCNTR4_EL0},
+ {"pmevcntr5_el0", PMEVCNTR5_EL0},
+ {"pmevcntr6_el0", PMEVCNTR6_EL0},
+ {"pmevcntr7_el0", PMEVCNTR7_EL0},
+ {"pmevcntr8_el0", PMEVCNTR8_EL0},
+ {"pmevcntr9_el0", PMEVCNTR9_EL0},
+ {"pmevcntr10_el0", PMEVCNTR10_EL0},
+ {"pmevcntr11_el0", PMEVCNTR11_EL0},
+ {"pmevcntr12_el0", PMEVCNTR12_EL0},
+ {"pmevcntr13_el0", PMEVCNTR13_EL0},
+ {"pmevcntr14_el0", PMEVCNTR14_EL0},
+ {"pmevcntr15_el0", PMEVCNTR15_EL0},
+ {"pmevcntr16_el0", PMEVCNTR16_EL0},
+ {"pmevcntr17_el0", PMEVCNTR17_EL0},
+ {"pmevcntr18_el0", PMEVCNTR18_EL0},
+ {"pmevcntr19_el0", PMEVCNTR19_EL0},
+ {"pmevcntr20_el0", PMEVCNTR20_EL0},
+ {"pmevcntr21_el0", PMEVCNTR21_EL0},
+ {"pmevcntr22_el0", PMEVCNTR22_EL0},
+ {"pmevcntr23_el0", PMEVCNTR23_EL0},
+ {"pmevcntr24_el0", PMEVCNTR24_EL0},
+ {"pmevcntr25_el0", PMEVCNTR25_EL0},
+ {"pmevcntr26_el0", PMEVCNTR26_EL0},
+ {"pmevcntr27_el0", PMEVCNTR27_EL0},
+ {"pmevcntr28_el0", PMEVCNTR28_EL0},
+ {"pmevcntr29_el0", PMEVCNTR29_EL0},
+ {"pmevcntr30_el0", PMEVCNTR30_EL0},
+ {"pmccfiltr_el0", PMCCFILTR_EL0},
+ {"pmevtyper0_el0", PMEVTYPER0_EL0},
+ {"pmevtyper1_el0", PMEVTYPER1_EL0},
+ {"pmevtyper2_el0", PMEVTYPER2_EL0},
+ {"pmevtyper3_el0", PMEVTYPER3_EL0},
+ {"pmevtyper4_el0", PMEVTYPER4_EL0},
+ {"pmevtyper5_el0", PMEVTYPER5_EL0},
+ {"pmevtyper6_el0", PMEVTYPER6_EL0},
+ {"pmevtyper7_el0", PMEVTYPER7_EL0},
+ {"pmevtyper8_el0", PMEVTYPER8_EL0},
+ {"pmevtyper9_el0", PMEVTYPER9_EL0},
+ {"pmevtyper10_el0", PMEVTYPER10_EL0},
+ {"pmevtyper11_el0", PMEVTYPER11_EL0},
+ {"pmevtyper12_el0", PMEVTYPER12_EL0},
+ {"pmevtyper13_el0", PMEVTYPER13_EL0},
+ {"pmevtyper14_el0", PMEVTYPER14_EL0},
+ {"pmevtyper15_el0", PMEVTYPER15_EL0},
+ {"pmevtyper16_el0", PMEVTYPER16_EL0},
+ {"pmevtyper17_el0", PMEVTYPER17_EL0},
+ {"pmevtyper18_el0", PMEVTYPER18_EL0},
+ {"pmevtyper19_el0", PMEVTYPER19_EL0},
+ {"pmevtyper20_el0", PMEVTYPER20_EL0},
+ {"pmevtyper21_el0", PMEVTYPER21_EL0},
+ {"pmevtyper22_el0", PMEVTYPER22_EL0},
+ {"pmevtyper23_el0", PMEVTYPER23_EL0},
+ {"pmevtyper24_el0", PMEVTYPER24_EL0},
+ {"pmevtyper25_el0", PMEVTYPER25_EL0},
+ {"pmevtyper26_el0", PMEVTYPER26_EL0},
+ {"pmevtyper27_el0", PMEVTYPER27_EL0},
+ {"pmevtyper28_el0", PMEVTYPER28_EL0},
+ {"pmevtyper29_el0", PMEVTYPER29_EL0},
+ {"pmevtyper30_el0", PMEVTYPER30_EL0},
+
+ // Trace registers
+ {"trcprgctlr", TRCPRGCTLR},
+ {"trcprocselr", TRCPROCSELR},
+ {"trcconfigr", TRCCONFIGR},
+ {"trcauxctlr", TRCAUXCTLR},
+ {"trceventctl0r", TRCEVENTCTL0R},
+ {"trceventctl1r", TRCEVENTCTL1R},
+ {"trcstallctlr", TRCSTALLCTLR},
+ {"trctsctlr", TRCTSCTLR},
+ {"trcsyncpr", TRCSYNCPR},
+ {"trcccctlr", TRCCCCTLR},
+ {"trcbbctlr", TRCBBCTLR},
+ {"trctraceidr", TRCTRACEIDR},
+ {"trcqctlr", TRCQCTLR},
+ {"trcvictlr", TRCVICTLR},
+ {"trcviiectlr", TRCVIIECTLR},
+ {"trcvissctlr", TRCVISSCTLR},
+ {"trcvipcssctlr", TRCVIPCSSCTLR},
+ {"trcvdctlr", TRCVDCTLR},
+ {"trcvdsacctlr", TRCVDSACCTLR},
+ {"trcvdarcctlr", TRCVDARCCTLR},
+ {"trcseqevr0", TRCSEQEVR0},
+ {"trcseqevr1", TRCSEQEVR1},
+ {"trcseqevr2", TRCSEQEVR2},
+ {"trcseqrstevr", TRCSEQRSTEVR},
+ {"trcseqstr", TRCSEQSTR},
+ {"trcextinselr", TRCEXTINSELR},
+ {"trccntrldvr0", TRCCNTRLDVR0},
+ {"trccntrldvr1", TRCCNTRLDVR1},
+ {"trccntrldvr2", TRCCNTRLDVR2},
+ {"trccntrldvr3", TRCCNTRLDVR3},
+ {"trccntctlr0", TRCCNTCTLR0},
+ {"trccntctlr1", TRCCNTCTLR1},
+ {"trccntctlr2", TRCCNTCTLR2},
+ {"trccntctlr3", TRCCNTCTLR3},
+ {"trccntvr0", TRCCNTVR0},
+ {"trccntvr1", TRCCNTVR1},
+ {"trccntvr2", TRCCNTVR2},
+ {"trccntvr3", TRCCNTVR3},
+ {"trcimspec0", TRCIMSPEC0},
+ {"trcimspec1", TRCIMSPEC1},
+ {"trcimspec2", TRCIMSPEC2},
+ {"trcimspec3", TRCIMSPEC3},
+ {"trcimspec4", TRCIMSPEC4},
+ {"trcimspec5", TRCIMSPEC5},
+ {"trcimspec6", TRCIMSPEC6},
+ {"trcimspec7", TRCIMSPEC7},
+ {"trcrsctlr2", TRCRSCTLR2},
+ {"trcrsctlr3", TRCRSCTLR3},
+ {"trcrsctlr4", TRCRSCTLR4},
+ {"trcrsctlr5", TRCRSCTLR5},
+ {"trcrsctlr6", TRCRSCTLR6},
+ {"trcrsctlr7", TRCRSCTLR7},
+ {"trcrsctlr8", TRCRSCTLR8},
+ {"trcrsctlr9", TRCRSCTLR9},
+ {"trcrsctlr10", TRCRSCTLR10},
+ {"trcrsctlr11", TRCRSCTLR11},
+ {"trcrsctlr12", TRCRSCTLR12},
+ {"trcrsctlr13", TRCRSCTLR13},
+ {"trcrsctlr14", TRCRSCTLR14},
+ {"trcrsctlr15", TRCRSCTLR15},
+ {"trcrsctlr16", TRCRSCTLR16},
+ {"trcrsctlr17", TRCRSCTLR17},
+ {"trcrsctlr18", TRCRSCTLR18},
+ {"trcrsctlr19", TRCRSCTLR19},
+ {"trcrsctlr20", TRCRSCTLR20},
+ {"trcrsctlr21", TRCRSCTLR21},
+ {"trcrsctlr22", TRCRSCTLR22},
+ {"trcrsctlr23", TRCRSCTLR23},
+ {"trcrsctlr24", TRCRSCTLR24},
+ {"trcrsctlr25", TRCRSCTLR25},
+ {"trcrsctlr26", TRCRSCTLR26},
+ {"trcrsctlr27", TRCRSCTLR27},
+ {"trcrsctlr28", TRCRSCTLR28},
+ {"trcrsctlr29", TRCRSCTLR29},
+ {"trcrsctlr30", TRCRSCTLR30},
+ {"trcrsctlr31", TRCRSCTLR31},
+ {"trcssccr0", TRCSSCCR0},
+ {"trcssccr1", TRCSSCCR1},
+ {"trcssccr2", TRCSSCCR2},
+ {"trcssccr3", TRCSSCCR3},
+ {"trcssccr4", TRCSSCCR4},
+ {"trcssccr5", TRCSSCCR5},
+ {"trcssccr6", TRCSSCCR6},
+ {"trcssccr7", TRCSSCCR7},
+ {"trcsscsr0", TRCSSCSR0},
+ {"trcsscsr1", TRCSSCSR1},
+ {"trcsscsr2", TRCSSCSR2},
+ {"trcsscsr3", TRCSSCSR3},
+ {"trcsscsr4", TRCSSCSR4},
+ {"trcsscsr5", TRCSSCSR5},
+ {"trcsscsr6", TRCSSCSR6},
+ {"trcsscsr7", TRCSSCSR7},
+ {"trcsspcicr0", TRCSSPCICR0},
+ {"trcsspcicr1", TRCSSPCICR1},
+ {"trcsspcicr2", TRCSSPCICR2},
+ {"trcsspcicr3", TRCSSPCICR3},
+ {"trcsspcicr4", TRCSSPCICR4},
+ {"trcsspcicr5", TRCSSPCICR5},
+ {"trcsspcicr6", TRCSSPCICR6},
+ {"trcsspcicr7", TRCSSPCICR7},
+ {"trcpdcr", TRCPDCR},
+ {"trcacvr0", TRCACVR0},
+ {"trcacvr1", TRCACVR1},
+ {"trcacvr2", TRCACVR2},
+ {"trcacvr3", TRCACVR3},
+ {"trcacvr4", TRCACVR4},
+ {"trcacvr5", TRCACVR5},
+ {"trcacvr6", TRCACVR6},
+ {"trcacvr7", TRCACVR7},
+ {"trcacvr8", TRCACVR8},
+ {"trcacvr9", TRCACVR9},
+ {"trcacvr10", TRCACVR10},
+ {"trcacvr11", TRCACVR11},
+ {"trcacvr12", TRCACVR12},
+ {"trcacvr13", TRCACVR13},
+ {"trcacvr14", TRCACVR14},
+ {"trcacvr15", TRCACVR15},
+ {"trcacatr0", TRCACATR0},
+ {"trcacatr1", TRCACATR1},
+ {"trcacatr2", TRCACATR2},
+ {"trcacatr3", TRCACATR3},
+ {"trcacatr4", TRCACATR4},
+ {"trcacatr5", TRCACATR5},
+ {"trcacatr6", TRCACATR6},
+ {"trcacatr7", TRCACATR7},
+ {"trcacatr8", TRCACATR8},
+ {"trcacatr9", TRCACATR9},
+ {"trcacatr10", TRCACATR10},
+ {"trcacatr11", TRCACATR11},
+ {"trcacatr12", TRCACATR12},
+ {"trcacatr13", TRCACATR13},
+ {"trcacatr14", TRCACATR14},
+ {"trcacatr15", TRCACATR15},
+ {"trcdvcvr0", TRCDVCVR0},
+ {"trcdvcvr1", TRCDVCVR1},
+ {"trcdvcvr2", TRCDVCVR2},
+ {"trcdvcvr3", TRCDVCVR3},
+ {"trcdvcvr4", TRCDVCVR4},
+ {"trcdvcvr5", TRCDVCVR5},
+ {"trcdvcvr6", TRCDVCVR6},
+ {"trcdvcvr7", TRCDVCVR7},
+ {"trcdvcmr0", TRCDVCMR0},
+ {"trcdvcmr1", TRCDVCMR1},
+ {"trcdvcmr2", TRCDVCMR2},
+ {"trcdvcmr3", TRCDVCMR3},
+ {"trcdvcmr4", TRCDVCMR4},
+ {"trcdvcmr5", TRCDVCMR5},
+ {"trcdvcmr6", TRCDVCMR6},
+ {"trcdvcmr7", TRCDVCMR7},
+ {"trccidcvr0", TRCCIDCVR0},
+ {"trccidcvr1", TRCCIDCVR1},
+ {"trccidcvr2", TRCCIDCVR2},
+ {"trccidcvr3", TRCCIDCVR3},
+ {"trccidcvr4", TRCCIDCVR4},
+ {"trccidcvr5", TRCCIDCVR5},
+ {"trccidcvr6", TRCCIDCVR6},
+ {"trccidcvr7", TRCCIDCVR7},
+ {"trcvmidcvr0", TRCVMIDCVR0},
+ {"trcvmidcvr1", TRCVMIDCVR1},
+ {"trcvmidcvr2", TRCVMIDCVR2},
+ {"trcvmidcvr3", TRCVMIDCVR3},
+ {"trcvmidcvr4", TRCVMIDCVR4},
+ {"trcvmidcvr5", TRCVMIDCVR5},
+ {"trcvmidcvr6", TRCVMIDCVR6},
+ {"trcvmidcvr7", TRCVMIDCVR7},
+ {"trccidcctlr0", TRCCIDCCTLR0},
+ {"trccidcctlr1", TRCCIDCCTLR1},
+ {"trcvmidcctlr0", TRCVMIDCCTLR0},
+ {"trcvmidcctlr1", TRCVMIDCCTLR1},
+ {"trcitctrl", TRCITCTRL},
+ {"trcclaimset", TRCCLAIMSET},
+ {"trcclaimclr", TRCCLAIMCLR},
+
+ // GICv3 registers
+ {"icc_bpr1_el1", ICC_BPR1_EL1},
+ {"icc_bpr0_el1", ICC_BPR0_EL1},
+ {"icc_pmr_el1", ICC_PMR_EL1},
+ {"icc_ctlr_el1", ICC_CTLR_EL1},
+ {"icc_ctlr_el3", ICC_CTLR_EL3},
+ {"icc_sre_el1", ICC_SRE_EL1},
+ {"icc_sre_el2", ICC_SRE_EL2},
+ {"icc_sre_el3", ICC_SRE_EL3},
+ {"icc_igrpen0_el1", ICC_IGRPEN0_EL1},
+ {"icc_igrpen1_el1", ICC_IGRPEN1_EL1},
+ {"icc_igrpen1_el3", ICC_IGRPEN1_EL3},
+ {"icc_seien_el1", ICC_SEIEN_EL1},
+ {"icc_ap0r0_el1", ICC_AP0R0_EL1},
+ {"icc_ap0r1_el1", ICC_AP0R1_EL1},
+ {"icc_ap0r2_el1", ICC_AP0R2_EL1},
+ {"icc_ap0r3_el1", ICC_AP0R3_EL1},
+ {"icc_ap1r0_el1", ICC_AP1R0_EL1},
+ {"icc_ap1r1_el1", ICC_AP1R1_EL1},
+ {"icc_ap1r2_el1", ICC_AP1R2_EL1},
+ {"icc_ap1r3_el1", ICC_AP1R3_EL1},
+ {"ich_ap0r0_el2", ICH_AP0R0_EL2},
+ {"ich_ap0r1_el2", ICH_AP0R1_EL2},
+ {"ich_ap0r2_el2", ICH_AP0R2_EL2},
+ {"ich_ap0r3_el2", ICH_AP0R3_EL2},
+ {"ich_ap1r0_el2", ICH_AP1R0_EL2},
+ {"ich_ap1r1_el2", ICH_AP1R1_EL2},
+ {"ich_ap1r2_el2", ICH_AP1R2_EL2},
+ {"ich_ap1r3_el2", ICH_AP1R3_EL2},
+ {"ich_hcr_el2", ICH_HCR_EL2},
+ {"ich_misr_el2", ICH_MISR_EL2},
+ {"ich_vmcr_el2", ICH_VMCR_EL2},
+ {"ich_vseir_el2", ICH_VSEIR_EL2},
+ {"ich_lr0_el2", ICH_LR0_EL2},
+ {"ich_lr1_el2", ICH_LR1_EL2},
+ {"ich_lr2_el2", ICH_LR2_EL2},
+ {"ich_lr3_el2", ICH_LR3_EL2},
+ {"ich_lr4_el2", ICH_LR4_EL2},
+ {"ich_lr5_el2", ICH_LR5_EL2},
+ {"ich_lr6_el2", ICH_LR6_EL2},
+ {"ich_lr7_el2", ICH_LR7_EL2},
+ {"ich_lr8_el2", ICH_LR8_EL2},
+ {"ich_lr9_el2", ICH_LR9_EL2},
+ {"ich_lr10_el2", ICH_LR10_EL2},
+ {"ich_lr11_el2", ICH_LR11_EL2},
+ {"ich_lr12_el2", ICH_LR12_EL2},
+ {"ich_lr13_el2", ICH_LR13_EL2},
+ {"ich_lr14_el2", ICH_LR14_EL2},
+ {"ich_lr15_el2", ICH_LR15_EL2},
+ {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3}
+};
+
+uint32_t
+ARM64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const {
+ // First search the registers shared by all
+ std::string NameLower = Name.lower();
+ for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
+ if (SysRegPairs[i].Name == NameLower) {
+ Valid = true;
+ return SysRegPairs[i].Value;
+ }
+ }
+
+ // Now try the instruction-specific registers (either read-only or
+ // write-only).
+ for (unsigned i = 0; i < NumInstPairs; ++i) {
+ if (InstPairs[i].Name == NameLower) {
+ Valid = true;
+ return InstPairs[i].Value;
+ }
+ }
+
+ // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits
+ // are: 11 xxx 1x11 xxxx xxx
+ Regex GenericRegPattern("^s3_([0-7])_c(1[15])_c([0-9]|1[0-5])_([0-7])$");
+
+ SmallVector<StringRef, 4> Ops;
+ if (!GenericRegPattern.match(NameLower, &Ops)) {
+ Valid = false;
+ return -1;
+ }
+
+ uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
+ uint32_t Bits;
+ Ops[1].getAsInteger(10, Op1);
+ Ops[2].getAsInteger(10, CRn);
+ Ops[3].getAsInteger(10, CRm);
+ Ops[4].getAsInteger(10, Op2);
+ Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
+
+ Valid = true;
+ return Bits;
+}
+
+std::string
+ARM64SysReg::SysRegMapper::toString(uint32_t Bits, bool &Valid) const {
+ for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
+ if (SysRegPairs[i].Value == Bits) {
+ Valid = true;
+ return SysRegPairs[i].Name;
+ }
+ }
+
+ for (unsigned i = 0; i < NumInstPairs; ++i) {
+ if (InstPairs[i].Value == Bits) {
+ Valid = true;
+ return InstPairs[i].Name;
+ }
+ }
+
+ uint32_t Op0 = (Bits >> 14) & 0x3;
+ uint32_t Op1 = (Bits >> 11) & 0x7;
+ uint32_t CRn = (Bits >> 7) & 0xf;
+ uint32_t CRm = (Bits >> 3) & 0xf;
+ uint32_t Op2 = Bits & 0x7;
+
+ // Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic
+ // name.
+ if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
+ Valid = false;
+ return "";
+ }
+
+ assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
+
+ Valid = true;
+ return "s3_" + utostr(Op1) + "_c" + utostr(CRn)
+ + "_c" + utostr(CRm) + "_" + utostr(Op2);
+}
+
+const ARM64NamedImmMapper::Mapping ARM64TLBI::TLBIMapper::TLBIPairs[] = {
+ {"ipas2e1is", IPAS2E1IS},
+ {"ipas2le1is", IPAS2LE1IS},
+ {"vmalle1is", VMALLE1IS},
+ {"alle2is", ALLE2IS},
+ {"alle3is", ALLE3IS},
+ {"vae1is", VAE1IS},
+ {"vae2is", VAE2IS},
+ {"vae3is", VAE3IS},
+ {"aside1is", ASIDE1IS},
+ {"vaae1is", VAAE1IS},
+ {"alle1is", ALLE1IS},
+ {"vale1is", VALE1IS},
+ {"vale2is", VALE2IS},
+ {"vale3is", VALE3IS},
+ {"vmalls12e1is", VMALLS12E1IS},
+ {"vaale1is", VAALE1IS},
+ {"ipas2e1", IPAS2E1},
+ {"ipas2le1", IPAS2LE1},
+ {"vmalle1", VMALLE1},
+ {"alle2", ALLE2},
+ {"alle3", ALLE3},
+ {"vae1", VAE1},
+ {"vae2", VAE2},
+ {"vae3", VAE3},
+ {"aside1", ASIDE1},
+ {"vaae1", VAAE1},
+ {"alle1", ALLE1},
+ {"vale1", VALE1},
+ {"vale2", VALE2},
+ {"vale3", VALE3},
+ {"vmalls12e1", VMALLS12E1},
+ {"vaale1", VAALE1}
+};
+
+ARM64TLBI::TLBIMapper::TLBIMapper()
+ : ARM64NamedImmMapper(TLBIPairs, 0) {}
diff --git a/lib/Target/ARM64/Utils/ARM64BaseInfo.h b/lib/Target/ARM64/Utils/ARM64BaseInfo.h
new file mode 100644
index 0000000..66c2052
--- /dev/null
+++ b/lib/Target/ARM64/Utils/ARM64BaseInfo.h
@@ -0,0 +1,1290 @@
+//===-- ARM64BaseInfo.h - Top level definitions for ARM64 -------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the ARM64 target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef ARM64BASEINFO_H
+#define ARM64BASEINFO_H
+
+// FIXME: Is it easiest to fix this layering violation by moving the .inc
+// #includes from ARM64MCTargetDesc.h to here?
+#include "MCTargetDesc/ARM64MCTargetDesc.h" // For ARM64::X0 and friends.
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/Support/ErrorHandling.h"
+
+namespace llvm {
+
+inline static unsigned getWRegFromXReg(unsigned Reg) {
+ switch (Reg) {
+ case ARM64::X0: return ARM64::W0;
+ case ARM64::X1: return ARM64::W1;
+ case ARM64::X2: return ARM64::W2;
+ case ARM64::X3: return ARM64::W3;
+ case ARM64::X4: return ARM64::W4;
+ case ARM64::X5: return ARM64::W5;
+ case ARM64::X6: return ARM64::W6;
+ case ARM64::X7: return ARM64::W7;
+ case ARM64::X8: return ARM64::W8;
+ case ARM64::X9: return ARM64::W9;
+ case ARM64::X10: return ARM64::W10;
+ case ARM64::X11: return ARM64::W11;
+ case ARM64::X12: return ARM64::W12;
+ case ARM64::X13: return ARM64::W13;
+ case ARM64::X14: return ARM64::W14;
+ case ARM64::X15: return ARM64::W15;
+ case ARM64::X16: return ARM64::W16;
+ case ARM64::X17: return ARM64::W17;
+ case ARM64::X18: return ARM64::W18;
+ case ARM64::X19: return ARM64::W19;
+ case ARM64::X20: return ARM64::W20;
+ case ARM64::X21: return ARM64::W21;
+ case ARM64::X22: return ARM64::W22;
+ case ARM64::X23: return ARM64::W23;
+ case ARM64::X24: return ARM64::W24;
+ case ARM64::X25: return ARM64::W25;
+ case ARM64::X26: return ARM64::W26;
+ case ARM64::X27: return ARM64::W27;
+ case ARM64::X28: return ARM64::W28;
+ case ARM64::FP: return ARM64::W29;
+ case ARM64::LR: return ARM64::W30;
+ case ARM64::SP: return ARM64::WSP;
+ case ARM64::XZR: return ARM64::WZR;
+ }
+ // For anything else, return it unchanged.
+ return Reg;
+}
+
+inline static unsigned getXRegFromWReg(unsigned Reg) {
+ switch (Reg) {
+ case ARM64::W0: return ARM64::X0;
+ case ARM64::W1: return ARM64::X1;
+ case ARM64::W2: return ARM64::X2;
+ case ARM64::W3: return ARM64::X3;
+ case ARM64::W4: return ARM64::X4;
+ case ARM64::W5: return ARM64::X5;
+ case ARM64::W6: return ARM64::X6;
+ case ARM64::W7: return ARM64::X7;
+ case ARM64::W8: return ARM64::X8;
+ case ARM64::W9: return ARM64::X9;
+ case ARM64::W10: return ARM64::X10;
+ case ARM64::W11: return ARM64::X11;
+ case ARM64::W12: return ARM64::X12;
+ case ARM64::W13: return ARM64::X13;
+ case ARM64::W14: return ARM64::X14;
+ case ARM64::W15: return ARM64::X15;
+ case ARM64::W16: return ARM64::X16;
+ case ARM64::W17: return ARM64::X17;
+ case ARM64::W18: return ARM64::X18;
+ case ARM64::W19: return ARM64::X19;
+ case ARM64::W20: return ARM64::X20;
+ case ARM64::W21: return ARM64::X21;
+ case ARM64::W22: return ARM64::X22;
+ case ARM64::W23: return ARM64::X23;
+ case ARM64::W24: return ARM64::X24;
+ case ARM64::W25: return ARM64::X25;
+ case ARM64::W26: return ARM64::X26;
+ case ARM64::W27: return ARM64::X27;
+ case ARM64::W28: return ARM64::X28;
+ case ARM64::W29: return ARM64::FP;
+ case ARM64::W30: return ARM64::LR;
+ case ARM64::WSP: return ARM64::SP;
+ case ARM64::WZR: return ARM64::XZR;
+ }
+ // For anything else, return it unchanged.
+ return Reg;
+}
+
+static inline unsigned getBRegFromDReg(unsigned Reg) {
+ switch (Reg) {
+ case ARM64::D0: return ARM64::B0;
+ case ARM64::D1: return ARM64::B1;
+ case ARM64::D2: return ARM64::B2;
+ case ARM64::D3: return ARM64::B3;
+ case ARM64::D4: return ARM64::B4;
+ case ARM64::D5: return ARM64::B5;
+ case ARM64::D6: return ARM64::B6;
+ case ARM64::D7: return ARM64::B7;
+ case ARM64::D8: return ARM64::B8;
+ case ARM64::D9: return ARM64::B9;
+ case ARM64::D10: return ARM64::B10;
+ case ARM64::D11: return ARM64::B11;
+ case ARM64::D12: return ARM64::B12;
+ case ARM64::D13: return ARM64::B13;
+ case ARM64::D14: return ARM64::B14;
+ case ARM64::D15: return ARM64::B15;
+ case ARM64::D16: return ARM64::B16;
+ case ARM64::D17: return ARM64::B17;
+ case ARM64::D18: return ARM64::B18;
+ case ARM64::D19: return ARM64::B19;
+ case ARM64::D20: return ARM64::B20;
+ case ARM64::D21: return ARM64::B21;
+ case ARM64::D22: return ARM64::B22;
+ case ARM64::D23: return ARM64::B23;
+ case ARM64::D24: return ARM64::B24;
+ case ARM64::D25: return ARM64::B25;
+ case ARM64::D26: return ARM64::B26;
+ case ARM64::D27: return ARM64::B27;
+ case ARM64::D28: return ARM64::B28;
+ case ARM64::D29: return ARM64::B29;
+ case ARM64::D30: return ARM64::B30;
+ case ARM64::D31: return ARM64::B31;
+ }
+ // For anything else, return it unchanged.
+ return Reg;
+}
+
+
+static inline unsigned getDRegFromBReg(unsigned Reg) {
+ switch (Reg) {
+ case ARM64::B0: return ARM64::D0;
+ case ARM64::B1: return ARM64::D1;
+ case ARM64::B2: return ARM64::D2;
+ case ARM64::B3: return ARM64::D3;
+ case ARM64::B4: return ARM64::D4;
+ case ARM64::B5: return ARM64::D5;
+ case ARM64::B6: return ARM64::D6;
+ case ARM64::B7: return ARM64::D7;
+ case ARM64::B8: return ARM64::D8;
+ case ARM64::B9: return ARM64::D9;
+ case ARM64::B10: return ARM64::D10;
+ case ARM64::B11: return ARM64::D11;
+ case ARM64::B12: return ARM64::D12;
+ case ARM64::B13: return ARM64::D13;
+ case ARM64::B14: return ARM64::D14;
+ case ARM64::B15: return ARM64::D15;
+ case ARM64::B16: return ARM64::D16;
+ case ARM64::B17: return ARM64::D17;
+ case ARM64::B18: return ARM64::D18;
+ case ARM64::B19: return ARM64::D19;
+ case ARM64::B20: return ARM64::D20;
+ case ARM64::B21: return ARM64::D21;
+ case ARM64::B22: return ARM64::D22;
+ case ARM64::B23: return ARM64::D23;
+ case ARM64::B24: return ARM64::D24;
+ case ARM64::B25: return ARM64::D25;
+ case ARM64::B26: return ARM64::D26;
+ case ARM64::B27: return ARM64::D27;
+ case ARM64::B28: return ARM64::D28;
+ case ARM64::B29: return ARM64::D29;
+ case ARM64::B30: return ARM64::D30;
+ case ARM64::B31: return ARM64::D31;
+ }
+ // For anything else, return it unchanged.
+ return Reg;
+}
+
+namespace ARM64CC {
+
+// The CondCodes constants map directly to the 4-bit encoding of the condition
+// field for predicated instructions.
+enum CondCode { // Meaning (integer) Meaning (floating-point)
+ EQ = 0x0, // Equal Equal
+ NE = 0x1, // Not equal Not equal, or unordered
+ CS = 0x2, // Carry set >, ==, or unordered
+ CC = 0x3, // Carry clear Less than
+ MI = 0x4, // Minus, negative Less than
+ PL = 0x5, // Plus, positive or zero >, ==, or unordered
+ VS = 0x6, // Overflow Unordered
+ VC = 0x7, // No overflow Not unordered
+ HI = 0x8, // Unsigned higher Greater than, or unordered
+ LS = 0x9, // Unsigned lower or same Less than or equal
+ GE = 0xa, // Greater than or equal Greater than or equal
+ LT = 0xb, // Less than Less than, or unordered
+ GT = 0xc, // Greater than Greater than
+ LE = 0xd, // Less than or equal <, ==, or unordered
+ AL = 0xe, // Always (unconditional) Always (unconditional)
+ NV = 0xf, // Always (unconditional) Always (unconditional)
+ // Note the NV exists purely to disassemble 0b1111. Execution is "always".
+ Invalid
+};
+
+inline static const char *getCondCodeName(CondCode Code) {
+ switch (Code) {
+ default: llvm_unreachable("Unknown condition code");
+ case EQ: return "eq";
+ case NE: return "ne";
+ case CS: return "cs";
+ case CC: return "cc";
+ case MI: return "mi";
+ case PL: return "pl";
+ case VS: return "vs";
+ case VC: return "vc";
+ case HI: return "hi";
+ case LS: return "ls";
+ case GE: return "ge";
+ case LT: return "lt";
+ case GT: return "gt";
+ case LE: return "le";
+ case AL: return "al";
+ case NV: return "nv";
+ }
+}
+
+inline static CondCode getInvertedCondCode(CondCode Code) {
+ switch (Code) {
+ default: llvm_unreachable("Unknown condition code");
+ case EQ: return NE;
+ case NE: return EQ;
+ case CS: return CC;
+ case CC: return CS;
+ case MI: return PL;
+ case PL: return MI;
+ case VS: return VC;
+ case VC: return VS;
+ case HI: return LS;
+ case LS: return HI;
+ case GE: return LT;
+ case LT: return GE;
+ case GT: return LE;
+ case LE: return GT;
+ }
+}
+
+/// Given a condition code, return NZCV flags that would satisfy that condition.
+/// The flag bits are in the format expected by the ccmp instructions.
+/// Note that many different flag settings can satisfy a given condition code,
+/// this function just returns one of them.
+inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
+ // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
+ enum { N = 8, Z = 4, C = 2, V = 1 };
+ switch (Code) {
+ default: llvm_unreachable("Unknown condition code");
+ case EQ: return Z; // Z == 1
+ case NE: return 0; // Z == 0
+ case CS: return C; // C == 1
+ case CC: return 0; // C == 0
+ case MI: return N; // N == 1
+ case PL: return 0; // N == 0
+ case VS: return V; // V == 1
+ case VC: return 0; // V == 0
+ case HI: return C; // C == 1 && Z == 0
+ case LS: return 0; // C == 0 || Z == 1
+ case GE: return 0; // N == V
+ case LT: return N; // N != V
+ case GT: return 0; // Z == 0 && N == V
+ case LE: return Z; // Z == 1 || N != V
+ }
+}
+} // end namespace ARM64CC
+
+/// Instances of this class can perform bidirectional mapping from random
+/// identifier strings to operand encodings. For example "MSR" takes a named
+/// system-register which must be encoded somehow and decoded for printing. This
+/// central location means that the information for those transformations is not
+/// duplicated and remains in sync.
+///
+/// FIXME: currently the algorithm is a completely unoptimised linear
+/// search. Obviously this could be improved, but we would probably want to work
+/// out just how often these instructions are emitted before working on it. It
+/// might even be optimal to just reorder the tables for the common instructions
+/// rather than changing the algorithm.
+struct ARM64NamedImmMapper {
+ struct Mapping {
+ const char *Name;
+ uint32_t Value;
+ };
+
+ template<int N>
+ ARM64NamedImmMapper(const Mapping (&Pairs)[N], uint32_t TooBigImm)
+ : Pairs(&Pairs[0]), NumPairs(N), TooBigImm(TooBigImm) {}
+
+ StringRef toString(uint32_t Value, bool &Valid) const;
+ uint32_t fromString(StringRef Name, bool &Valid) const;
+
+ /// Many of the instructions allow an alternative assembly form consisting of
+ /// a simple immediate. Currently the only valid forms are ranges [0, N) where
+ /// N being 0 indicates no immediate syntax-form is allowed.
+ bool validImm(uint32_t Value) const;
+protected:
+ const Mapping *Pairs;
+ size_t NumPairs;
+ uint32_t TooBigImm;
+};
+
+namespace ARM64AT {
+ enum ATValues {
+ Invalid = -1, // Op0 Op1 CRn CRm Op2
+ S1E1R = 0x43c0, // 01 000 0111 1000 000
+ S1E2R = 0x63c0, // 01 100 0111 1000 000
+ S1E3R = 0x73c0, // 01 110 0111 1000 000
+ S1E1W = 0x43c1, // 01 000 0111 1000 001
+ S1E2W = 0x63c1, // 01 100 0111 1000 001
+ S1E3W = 0x73c1, // 01 110 0111 1000 001
+ S1E0R = 0x43c2, // 01 000 0111 1000 010
+ S1E0W = 0x43c3, // 01 000 0111 1000 011
+ S12E1R = 0x63c4, // 01 100 0111 1000 100
+ S12E1W = 0x63c5, // 01 100 0111 1000 101
+ S12E0R = 0x63c6, // 01 100 0111 1000 110
+ S12E0W = 0x63c7 // 01 100 0111 1000 111
+ };
+
+ struct ATMapper : ARM64NamedImmMapper {
+ const static Mapping ATPairs[];
+
+ ATMapper();
+ };
+
+}
+namespace ARM64DB {
+ enum DBValues {
+ Invalid = -1,
+ OSHLD = 0x1,
+ OSHST = 0x2,
+ OSH = 0x3,
+ NSHLD = 0x5,
+ NSHST = 0x6,
+ NSH = 0x7,
+ ISHLD = 0x9,
+ ISHST = 0xa,
+ ISH = 0xb,
+ LD = 0xd,
+ ST = 0xe,
+ SY = 0xf
+ };
+
+ struct DBarrierMapper : ARM64NamedImmMapper {
+ const static Mapping DBarrierPairs[];
+
+ DBarrierMapper();
+ };
+}
+
+namespace ARM64DC {
+ enum DCValues {
+ Invalid = -1, // Op1 CRn CRm Op2
+ ZVA = 0x5ba1, // 01 011 0111 0100 001
+ IVAC = 0x43b1, // 01 000 0111 0110 001
+ ISW = 0x43b2, // 01 000 0111 0110 010
+ CVAC = 0x5bd1, // 01 011 0111 1010 001
+ CSW = 0x43d2, // 01 000 0111 1010 010
+ CVAU = 0x5bd9, // 01 011 0111 1011 001
+ CIVAC = 0x5bf1, // 01 011 0111 1110 001
+ CISW = 0x43f2 // 01 000 0111 1110 010
+ };
+
+ struct DCMapper : ARM64NamedImmMapper {
+ const static Mapping DCPairs[];
+
+ DCMapper();
+ };
+
+}
+
+namespace ARM64IC {
+ enum ICValues {
+ Invalid = -1, // Op1 CRn CRm Op2
+ IALLUIS = 0x0388, // 000 0111 0001 000
+ IALLU = 0x03a8, // 000 0111 0101 000
+ IVAU = 0x1ba9 // 011 0111 0101 001
+ };
+
+
+ struct ICMapper : ARM64NamedImmMapper {
+ const static Mapping ICPairs[];
+
+ ICMapper();
+ };
+
+ static inline bool NeedsRegister(ICValues Val) {
+ return Val == IVAU;
+ }
+}
+
+namespace ARM64ISB {
+ enum ISBValues {
+ Invalid = -1,
+ SY = 0xf
+ };
+ struct ISBMapper : ARM64NamedImmMapper {
+ const static Mapping ISBPairs[];
+
+ ISBMapper();
+ };
+}
+
+namespace ARM64PRFM {
+ enum PRFMValues {
+ Invalid = -1,
+ PLDL1KEEP = 0x00,
+ PLDL1STRM = 0x01,
+ PLDL2KEEP = 0x02,
+ PLDL2STRM = 0x03,
+ PLDL3KEEP = 0x04,
+ PLDL3STRM = 0x05,
+ PLIL1KEEP = 0x08,
+ PLIL1STRM = 0x09,
+ PLIL2KEEP = 0x0a,
+ PLIL2STRM = 0x0b,
+ PLIL3KEEP = 0x0c,
+ PLIL3STRM = 0x0d,
+ PSTL1KEEP = 0x10,
+ PSTL1STRM = 0x11,
+ PSTL2KEEP = 0x12,
+ PSTL2STRM = 0x13,
+ PSTL3KEEP = 0x14,
+ PSTL3STRM = 0x15
+ };
+
+ struct PRFMMapper : ARM64NamedImmMapper {
+ const static Mapping PRFMPairs[];
+
+ PRFMMapper();
+ };
+}
+
+namespace ARM64PState {
+ enum PStateValues {
+ Invalid = -1,
+ SPSel = 0x05,
+ DAIFSet = 0x1e,
+ DAIFClr = 0x1f
+ };
+
+ struct PStateMapper : ARM64NamedImmMapper {
+ const static Mapping PStatePairs[];
+
+ PStateMapper();
+ };
+
+}
+
+namespace ARM64SE {
+ enum ShiftExtSpecifiers {
+ Invalid = -1,
+ LSL,
+ MSL,
+ LSR,
+ ASR,
+ ROR,
+
+ UXTB,
+ UXTH,
+ UXTW,
+ UXTX,
+
+ SXTB,
+ SXTH,
+ SXTW,
+ SXTX
+ };
+}
+
+namespace ARM64Layout {
+ enum VectorLayout {
+ Invalid = -1,
+ VL_8B,
+ VL_4H,
+ VL_2S,
+ VL_1D,
+
+ VL_16B,
+ VL_8H,
+ VL_4S,
+ VL_2D,
+
+ // Bare layout for the 128-bit vector
+ // (only show ".b", ".h", ".s", ".d" without vector number)
+ VL_B,
+ VL_H,
+ VL_S,
+ VL_D
+ };
+}
+
+inline static const char *
+ARM64VectorLayoutToString(ARM64Layout::VectorLayout Layout) {
+ switch (Layout) {
+ case ARM64Layout::VL_8B: return ".8b";
+ case ARM64Layout::VL_4H: return ".4h";
+ case ARM64Layout::VL_2S: return ".2s";
+ case ARM64Layout::VL_1D: return ".1d";
+ case ARM64Layout::VL_16B: return ".16b";
+ case ARM64Layout::VL_8H: return ".8h";
+ case ARM64Layout::VL_4S: return ".4s";
+ case ARM64Layout::VL_2D: return ".2d";
+ case ARM64Layout::VL_B: return ".b";
+ case ARM64Layout::VL_H: return ".h";
+ case ARM64Layout::VL_S: return ".s";
+ case ARM64Layout::VL_D: return ".d";
+ default: llvm_unreachable("Unknown Vector Layout");
+ }
+}
+
+inline static ARM64Layout::VectorLayout
+ARM64StringToVectorLayout(StringRef LayoutStr) {
+ return StringSwitch<ARM64Layout::VectorLayout>(LayoutStr)
+ .Case(".8b", ARM64Layout::VL_8B)
+ .Case(".4h", ARM64Layout::VL_4H)
+ .Case(".2s", ARM64Layout::VL_2S)
+ .Case(".1d", ARM64Layout::VL_1D)
+ .Case(".16b", ARM64Layout::VL_16B)
+ .Case(".8h", ARM64Layout::VL_8H)
+ .Case(".4s", ARM64Layout::VL_4S)
+ .Case(".2d", ARM64Layout::VL_2D)
+ .Case(".b", ARM64Layout::VL_B)
+ .Case(".h", ARM64Layout::VL_H)
+ .Case(".s", ARM64Layout::VL_S)
+ .Case(".d", ARM64Layout::VL_D)
+ .Default(ARM64Layout::Invalid);
+}
+
+namespace ARM64SysReg {
+ enum SysRegROValues {
+ MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
+ DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
+ MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
+ OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
+ DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
+ PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
+ PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
+ MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
+ CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
+ CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
+ CTR_EL0 = 0xd801, // 11 011 0000 0000 001
+ MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
+ REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
+ AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
+ DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
+ ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
+ ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
+ ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
+ ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
+ ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
+ ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
+ ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
+ ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
+ ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
+ ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
+ ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
+ ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
+ ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
+ ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
+ ID_AARM64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
+ ID_AARM64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
+ ID_AARM64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
+ ID_AARM64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
+ ID_AARM64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
+ ID_AARM64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
+ ID_AARM64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
+ ID_AARM64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
+ ID_AARM64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
+ ID_AARM64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
+ MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
+ MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
+ MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
+ RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
+ RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
+ RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
+ ISR_EL1 = 0xc608, // 11 000 1100 0001 000
+ CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
+ CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
+
+ // Trace registers
+ TRCSTATR = 0x8818, // 10 001 0000 0011 000
+ TRCIDR8 = 0x8806, // 10 001 0000 0000 110
+ TRCIDR9 = 0x880e, // 10 001 0000 0001 110
+ TRCIDR10 = 0x8816, // 10 001 0000 0010 110
+ TRCIDR11 = 0x881e, // 10 001 0000 0011 110
+ TRCIDR12 = 0x8826, // 10 001 0000 0100 110
+ TRCIDR13 = 0x882e, // 10 001 0000 0101 110
+ TRCIDR0 = 0x8847, // 10 001 0000 1000 111
+ TRCIDR1 = 0x884f, // 10 001 0000 1001 111
+ TRCIDR2 = 0x8857, // 10 001 0000 1010 111
+ TRCIDR3 = 0x885f, // 10 001 0000 1011 111
+ TRCIDR4 = 0x8867, // 10 001 0000 1100 111
+ TRCIDR5 = 0x886f, // 10 001 0000 1101 111
+ TRCIDR6 = 0x8877, // 10 001 0000 1110 111
+ TRCIDR7 = 0x887f, // 10 001 0000 1111 111
+ TRCOSLSR = 0x888c, // 10 001 0001 0001 100
+ TRCPDSR = 0x88ac, // 10 001 0001 0101 100
+ TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
+ TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
+ TRCLSR = 0x8bee, // 10 001 0111 1101 110
+ TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
+ TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
+ TRCDEVID = 0x8b97, // 10 001 0111 0010 111
+ TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
+ TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
+ TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
+ TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
+ TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
+ TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
+ TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
+ TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
+ TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
+ TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
+ TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
+ TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
+ TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
+
+ // GICv3 registers
+ ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
+ ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
+ ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
+ ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
+ ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
+ ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
+ ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
+ ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
+ };
+
+ enum SysRegWOValues {
+ DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
+ OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
+ PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
+
+ // Trace Registers
+ TRCOSLAR = 0x8884, // 10 001 0001 0000 100
+ TRCLAR = 0x8be6, // 10 001 0111 1100 110
+
+ // GICv3 registers
+ ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
+ ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
+ ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
+ ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
+ ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
+ ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
+ };
+
+ enum SysRegValues {
+ Invalid = -1, // Op0 Op1 CRn CRm Op2
+ OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
+ OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
+ TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
+ MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
+ MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
+ DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
+ OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
+ DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
+ DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
+ DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
+ DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
+ DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
+ DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
+ DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
+ DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
+ DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
+ DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
+ DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
+ DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
+ DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
+ DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
+ DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
+ DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
+ DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
+ DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
+ DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
+ DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
+ DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
+ DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
+ DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
+ DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
+ DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
+ DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
+ DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
+ DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
+ DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
+ DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
+ DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
+ DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
+ DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
+ DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
+ DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
+ DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
+ DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
+ DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
+ DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
+ DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
+ DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
+ DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
+ DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
+ DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
+ DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
+ DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
+ DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
+ DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
+ DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
+ DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
+ DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
+ DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
+ DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
+ DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
+ DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
+ DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
+ DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
+ DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
+ DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
+ DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
+ DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
+ DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
+ DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
+ DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
+ DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
+ TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
+ OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
+ DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
+ DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
+ DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
+ CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
+ VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
+ VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
+ CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
+ SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
+ SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
+ SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
+ ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
+ ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
+ ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
+ HCR_EL2 = 0xe088, // 11 100 0001 0001 000
+ SCR_EL3 = 0xf088, // 11 110 0001 0001 000
+ MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
+ SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
+ CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
+ CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
+ HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
+ HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
+ MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
+ TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
+ TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
+ TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
+ TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
+ TCR_EL1 = 0xc102, // 11 000 0010 0000 010
+ TCR_EL2 = 0xe102, // 11 100 0010 0000 010
+ TCR_EL3 = 0xf102, // 11 110 0010 0000 010
+ VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
+ VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
+ DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
+ SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
+ SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
+ SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
+ ELR_EL1 = 0xc201, // 11 000 0100 0000 001
+ ELR_EL2 = 0xe201, // 11 100 0100 0000 001
+ ELR_EL3 = 0xf201, // 11 110 0100 0000 001
+ SP_EL0 = 0xc208, // 11 000 0100 0001 000
+ SP_EL1 = 0xe208, // 11 100 0100 0001 000
+ SP_EL2 = 0xf208, // 11 110 0100 0001 000
+ SPSel = 0xc210, // 11 000 0100 0010 000
+ NZCV = 0xda10, // 11 011 0100 0010 000
+ DAIF = 0xda11, // 11 011 0100 0010 001
+ CurrentEL = 0xc212, // 11 000 0100 0010 010
+ SPSR_irq = 0xe218, // 11 100 0100 0011 000
+ SPSR_abt = 0xe219, // 11 100 0100 0011 001
+ SPSR_und = 0xe21a, // 11 100 0100 0011 010
+ SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
+ FPCR = 0xda20, // 11 011 0100 0100 000
+ FPSR = 0xda21, // 11 011 0100 0100 001
+ DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
+ DLR_EL0 = 0xda29, // 11 011 0100 0101 001
+ IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
+ AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
+ AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
+ AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
+ AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
+ AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
+ AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
+ ESR_EL1 = 0xc290, // 11 000 0101 0010 000
+ ESR_EL2 = 0xe290, // 11 100 0101 0010 000
+ ESR_EL3 = 0xf290, // 11 110 0101 0010 000
+ FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
+ FAR_EL1 = 0xc300, // 11 000 0110 0000 000
+ FAR_EL2 = 0xe300, // 11 100 0110 0000 000
+ FAR_EL3 = 0xf300, // 11 110 0110 0000 000
+ HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
+ PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
+ PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
+ PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
+ PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
+ PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
+ PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
+ PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
+ PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
+ PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
+ PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
+ PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
+ PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
+ PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
+ MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
+ MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
+ MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
+ AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
+ AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
+ AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
+ VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
+ VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
+ VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
+ RMR_EL1 = 0xc602, // 11 000 1100 0000 010
+ RMR_EL2 = 0xe602, // 11 100 1100 0000 010
+ RMR_EL3 = 0xf602, // 11 110 1100 0000 010
+ CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
+ TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
+ TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
+ TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
+ TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
+ TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
+ CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
+ CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
+ CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
+ CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
+ CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
+ CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
+ CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
+ CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
+ CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
+ CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
+ CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
+ CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
+ CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
+ CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
+ CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
+ CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
+ PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
+ PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
+ PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
+ PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
+ PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
+ PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
+ PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
+ PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
+ PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
+ PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
+ PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
+ PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
+ PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
+ PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
+ PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
+ PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
+ PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
+ PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
+ PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
+ PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
+ PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
+ PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
+ PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
+ PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
+ PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
+ PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
+ PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
+ PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
+ PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
+ PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
+ PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
+ PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
+ PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
+ PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
+ PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
+ PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
+ PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
+ PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
+ PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
+ PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
+ PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
+ PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
+ PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
+ PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
+ PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
+ PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
+ PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
+ PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
+ PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
+ PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
+ PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
+ PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
+ PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
+ PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
+ PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
+ PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
+ PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
+ PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
+ PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
+ PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
+ PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
+ PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
+ PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
+
+ // Trace registers
+ TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
+ TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
+ TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
+ TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
+ TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
+ TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
+ TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
+ TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
+ TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
+ TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
+ TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
+ TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
+ TRCQCTLR = 0x8809, // 10 001 0000 0001 001
+ TRCVICTLR = 0x8802, // 10 001 0000 0000 010
+ TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
+ TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
+ TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
+ TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
+ TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
+ TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
+ TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
+ TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
+ TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
+ TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
+ TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
+ TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
+ TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
+ TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
+ TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
+ TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
+ TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
+ TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
+ TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
+ TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
+ TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
+ TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
+ TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
+ TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
+ TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
+ TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
+ TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
+ TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
+ TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
+ TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
+ TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
+ TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
+ TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
+ TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
+ TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
+ TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
+ TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
+ TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
+ TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
+ TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
+ TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
+ TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
+ TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
+ TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
+ TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
+ TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
+ TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
+ TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
+ TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
+ TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
+ TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
+ TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
+ TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
+ TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
+ TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
+ TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
+ TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
+ TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
+ TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
+ TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
+ TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
+ TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
+ TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
+ TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
+ TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
+ TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
+ TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
+ TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
+ TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
+ TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
+ TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
+ TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
+ TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
+ TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
+ TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
+ TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
+ TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
+ TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
+ TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
+ TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
+ TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
+ TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
+ TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
+ TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
+ TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
+ TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
+ TRCPDCR = 0x88a4, // 10 001 0001 0100 100
+ TRCACVR0 = 0x8900, // 10 001 0010 0000 000
+ TRCACVR1 = 0x8910, // 10 001 0010 0010 000
+ TRCACVR2 = 0x8920, // 10 001 0010 0100 000
+ TRCACVR3 = 0x8930, // 10 001 0010 0110 000
+ TRCACVR4 = 0x8940, // 10 001 0010 1000 000
+ TRCACVR5 = 0x8950, // 10 001 0010 1010 000
+ TRCACVR6 = 0x8960, // 10 001 0010 1100 000
+ TRCACVR7 = 0x8970, // 10 001 0010 1110 000
+ TRCACVR8 = 0x8901, // 10 001 0010 0000 001
+ TRCACVR9 = 0x8911, // 10 001 0010 0010 001
+ TRCACVR10 = 0x8921, // 10 001 0010 0100 001
+ TRCACVR11 = 0x8931, // 10 001 0010 0110 001
+ TRCACVR12 = 0x8941, // 10 001 0010 1000 001
+ TRCACVR13 = 0x8951, // 10 001 0010 1010 001
+ TRCACVR14 = 0x8961, // 10 001 0010 1100 001
+ TRCACVR15 = 0x8971, // 10 001 0010 1110 001
+ TRCACATR0 = 0x8902, // 10 001 0010 0000 010
+ TRCACATR1 = 0x8912, // 10 001 0010 0010 010
+ TRCACATR2 = 0x8922, // 10 001 0010 0100 010
+ TRCACATR3 = 0x8932, // 10 001 0010 0110 010
+ TRCACATR4 = 0x8942, // 10 001 0010 1000 010
+ TRCACATR5 = 0x8952, // 10 001 0010 1010 010
+ TRCACATR6 = 0x8962, // 10 001 0010 1100 010
+ TRCACATR7 = 0x8972, // 10 001 0010 1110 010
+ TRCACATR8 = 0x8903, // 10 001 0010 0000 011
+ TRCACATR9 = 0x8913, // 10 001 0010 0010 011
+ TRCACATR10 = 0x8923, // 10 001 0010 0100 011
+ TRCACATR11 = 0x8933, // 10 001 0010 0110 011
+ TRCACATR12 = 0x8943, // 10 001 0010 1000 011
+ TRCACATR13 = 0x8953, // 10 001 0010 1010 011
+ TRCACATR14 = 0x8963, // 10 001 0010 1100 011
+ TRCACATR15 = 0x8973, // 10 001 0010 1110 011
+ TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
+ TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
+ TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
+ TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
+ TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
+ TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
+ TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
+ TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
+ TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
+ TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
+ TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
+ TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
+ TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
+ TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
+ TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
+ TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
+ TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
+ TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
+ TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
+ TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
+ TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
+ TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
+ TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
+ TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
+ TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
+ TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
+ TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
+ TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
+ TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
+ TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
+ TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
+ TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
+ TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
+ TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
+ TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
+ TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
+ TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
+ TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
+ TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
+
+ // GICv3 registers
+ ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
+ ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
+ ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000
+ ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100
+ ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100
+ ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101
+ ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101
+ ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101
+ ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110
+ ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111
+ ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111
+ ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000
+ ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100
+ ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101
+ ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110
+ ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111
+ ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000
+ ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001
+ ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010
+ ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011
+ ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000
+ ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001
+ ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010
+ ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011
+ ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000
+ ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001
+ ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010
+ ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011
+ ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000
+ ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010
+ ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111
+ ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100
+ ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000
+ ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001
+ ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010
+ ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011
+ ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100
+ ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101
+ ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110
+ ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111
+ ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000
+ ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001
+ ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010
+ ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011
+ ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
+ ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
+ ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
+ ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111
+
+ // Cyclone specific system registers
+ CPM_IOACC_CTL_EL3 = 0xff90
+ };
+
+ // Note that these do not inherit from ARM64NamedImmMapper. This class is
+ // sufficiently different in its behaviour that I don't believe it's worth
+ // burdening the common ARM64NamedImmMapper with abstractions only needed in
+ // this one case.
+ struct SysRegMapper {
+ static const ARM64NamedImmMapper::Mapping SysRegPairs[];
+
+ const ARM64NamedImmMapper::Mapping *InstPairs;
+ size_t NumInstPairs;
+
+ SysRegMapper() {}
+ uint32_t fromString(StringRef Name, bool &Valid) const;
+ std::string toString(uint32_t Bits, bool &Valid) const;
+ };
+
+ struct MSRMapper : SysRegMapper {
+ static const ARM64NamedImmMapper::Mapping MSRPairs[];
+ MSRMapper();
+ };
+
+ struct MRSMapper : SysRegMapper {
+ static const ARM64NamedImmMapper::Mapping MRSPairs[];
+ MRSMapper();
+ };
+
+ uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
+}
+
+namespace ARM64TLBI {
+ enum TLBIValues {
+ Invalid = -1, // Op0 Op1 CRn CRm Op2
+ IPAS2E1IS = 0x6401, // 01 100 1000 0000 001
+ IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101
+ VMALLE1IS = 0x4418, // 01 000 1000 0011 000
+ ALLE2IS = 0x6418, // 01 100 1000 0011 000
+ ALLE3IS = 0x7418, // 01 110 1000 0011 000
+ VAE1IS = 0x4419, // 01 000 1000 0011 001
+ VAE2IS = 0x6419, // 01 100 1000 0011 001
+ VAE3IS = 0x7419, // 01 110 1000 0011 001
+ ASIDE1IS = 0x441a, // 01 000 1000 0011 010
+ VAAE1IS = 0x441b, // 01 000 1000 0011 011
+ ALLE1IS = 0x641c, // 01 100 1000 0011 100
+ VALE1IS = 0x441d, // 01 000 1000 0011 101
+ VALE2IS = 0x641d, // 01 100 1000 0011 101
+ VALE3IS = 0x741d, // 01 110 1000 0011 101
+ VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110
+ VAALE1IS = 0x441f, // 01 000 1000 0011 111
+ IPAS2E1 = 0x6421, // 01 100 1000 0100 001
+ IPAS2LE1 = 0x6425, // 01 100 1000 0100 101
+ VMALLE1 = 0x4438, // 01 000 1000 0111 000
+ ALLE2 = 0x6438, // 01 100 1000 0111 000
+ ALLE3 = 0x7438, // 01 110 1000 0111 000
+ VAE1 = 0x4439, // 01 000 1000 0111 001
+ VAE2 = 0x6439, // 01 100 1000 0111 001
+ VAE3 = 0x7439, // 01 110 1000 0111 001
+ ASIDE1 = 0x443a, // 01 000 1000 0111 010
+ VAAE1 = 0x443b, // 01 000 1000 0111 011
+ ALLE1 = 0x643c, // 01 100 1000 0111 100
+ VALE1 = 0x443d, // 01 000 1000 0111 101
+ VALE2 = 0x643d, // 01 100 1000 0111 101
+ VALE3 = 0x743d, // 01 110 1000 0111 101
+ VMALLS12E1 = 0x643e, // 01 100 1000 0111 110
+ VAALE1 = 0x443f // 01 000 1000 0111 111
+ };
+
+ struct TLBIMapper : ARM64NamedImmMapper {
+ const static Mapping TLBIPairs[];
+
+ TLBIMapper();
+ };
+
+ static inline bool NeedsRegister(TLBIValues Val) {
+ switch (Val) {
+ case VMALLE1IS:
+ case ALLE2IS:
+ case ALLE3IS:
+ case ALLE1IS:
+ case VMALLS12E1IS:
+ case VMALLE1:
+ case ALLE2:
+ case ALLE3:
+ case ALLE1:
+ case VMALLS12E1:
+ return false;
+ default:
+ return true;
+ }
+ }
+}
+
+namespace ARM64II {
+ /// Target Operand Flag enum.
+ enum TOF {
+ //===------------------------------------------------------------------===//
+ // ARM64 Specific MachineOperand flags.
+
+ MO_NO_FLAG,
+
+ MO_FRAGMENT = 0x7,
+
+ /// MO_PAGE - A symbol operand with this flag represents the pc-relative
+ /// offset of the 4K page containing the symbol. This is used with the
+ /// ADRP instruction.
+ MO_PAGE = 1,
+
+ /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
+ /// that symbol within a 4K page. This offset is added to the page address
+ /// to produce the complete address.
+ MO_PAGEOFF = 2,
+
+ /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
+ /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
+ MO_G3 = 3,
+
+ /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
+ /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
+ MO_G2 = 4,
+
+ /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
+ /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
+ MO_G1 = 5,
+
+ /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
+ /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
+ MO_G0 = 6,
+
+ /// MO_GOT - This flag indicates that a symbol operand represents the
+ /// address of the GOT entry for the symbol, rather than the address of
+ /// the symbol itself.
+ MO_GOT = 8,
+
+ /// MO_NC - Indicates whether the linker is expected to check the symbol
+ /// reference for overflow. For example in an ADRP/ADD pair of relocations
+ /// the ADRP usually does check, but not the ADD.
+ MO_NC = 0x10,
+
+ /// MO_TLS - Indicates that the operand being accessed is some kind of
+ /// thread-local symbol. On Darwin, only one type of thread-local access
+ /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
+ /// referee will affect interpretation.
+ MO_TLS = 0x20
+ };
+} // end namespace ARM64II
+
+} // end namespace llvm
+
+#endif
diff --git a/lib/Target/ARM64/Utils/CMakeLists.txt b/lib/Target/ARM64/Utils/CMakeLists.txt
new file mode 100644
index 0000000..f69076f
--- /dev/null
+++ b/lib/Target/ARM64/Utils/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_llvm_library(LLVMARM64Utils
+ ARM64BaseInfo.cpp
+ )
diff --git a/lib/Target/ARM64/Utils/LLVMBuild.txt b/lib/Target/ARM64/Utils/LLVMBuild.txt
new file mode 100644
index 0000000..232dca2
--- /dev/null
+++ b/lib/Target/ARM64/Utils/LLVMBuild.txt
@@ -0,0 +1,23 @@
+;===- ./lib/Target/ARM64/Utils/LLVMBuild.txt ----------------*- Conf -*--===;
+;
+; The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+; http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = ARM64Utils
+parent = ARM64
+required_libraries = Support
+add_to_library_groups = ARM64
diff --git a/lib/Target/ARM64/Utils/Makefile b/lib/Target/ARM64/Utils/Makefile
new file mode 100644
index 0000000..4bae80b
--- /dev/null
+++ b/lib/Target/ARM64/Utils/Makefile
@@ -0,0 +1,15 @@
+##===- lib/Target/ARM64/Utils/Makefile -------------------*- Makefile -*-===##
+#
+# The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+LEVEL = ../../../..
+LIBRARYNAME = LLVMARM64Utils
+
+# Hack: we need to include 'main' ARM64 target directory to grab private headers
+#CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
+
+include $(LEVEL)/Makefile.common
diff --git a/test/CodeGen/ARM64/aapcs.ll b/test/CodeGen/ARM64/aapcs.ll
index 27d2aa7..407ae07 100644
--- a/test/CodeGen/ARM64/aapcs.ll
+++ b/test/CodeGen/ARM64/aapcs.ll
@@ -57,7 +57,7 @@ define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
%ext_char = sext i8 %char to i64
store volatile i64 %ext_char, i64* @var64
-; CHECK: sxtb [[EXT:x[0-9]+]], x1
+; CHECK: sbfm [[EXT:x[0-9]+]], x1, #0, #7
; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
%ext_short = zext i16 %short to i64
@@ -67,7 +67,7 @@ define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
%ext_int = zext i32 %int to i64
store volatile i64 %ext_int, i64* @var64
-; CHECK: uxtw [[EXT:x[0-9]+]], x3
+; CHECK: ubfm [[EXT:x[0-9]+]], x3, #0, #31
; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
ret void
diff --git a/test/CodeGen/ARM64/abi.ll b/test/CodeGen/ARM64/abi.ll
index a7693b6..e2de434 100644
--- a/test/CodeGen/ARM64/abi.ll
+++ b/test/CodeGen/ARM64/abi.ll
@@ -77,6 +77,7 @@ entry:
; CHECK: fixed_4i
; CHECK: str [[REG_1:q[0-9]+]], [sp, #16]
; FAST: fixed_4i
+; FAST: sub sp, sp, #64
; FAST: mov x[[ADDR:[0-9]+]], sp
; FAST: str [[REG_1:q[0-9]+]], [x[[ADDR]], #16]
%0 = load <4 x i32>* %in, align 16
@@ -130,6 +131,7 @@ entry:
; CHECK: test3
; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
; FAST: test3
+; FAST: sub sp, sp, #32
; FAST: mov x[[ADDR:[0-9]+]], sp
; FAST: str [[REG_1:d[0-9]+]], [x[[ADDR]], #8]
%0 = load <2 x i32>* %in, align 8
diff --git a/test/CodeGen/ARM64/abi_align.ll b/test/CodeGen/ARM64/abi_align.ll
index 61c661e..d8ec395 100644
--- a/test/CodeGen/ARM64/abi_align.ll
+++ b/test/CodeGen/ARM64/abi_align.ll
@@ -294,7 +294,7 @@ entry:
; FAST: sub sp, sp, #96
; Space for s1 is allocated at fp-24 = sp+72
; Space for s2 is allocated at sp+48
-; FAST: sub x[[A:[0-9]+]], fp, #24
+; FAST: sub x[[A:[0-9]+]], x29, #24
; FAST: add x[[A:[0-9]+]], sp, #48
; Call memcpy with size = 24 (0x18)
; FAST: orr {{x[0-9]+}}, xzr, #0x18
@@ -317,17 +317,17 @@ declare i32 @f42_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
define i32 @caller42_stack() #3 {
entry:
; CHECK: caller42_stack
-; CHECK: mov fp, sp
+; CHECK: mov x29, sp
; CHECK: sub sp, sp, #96
-; CHECK: stur {{x[0-9]+}}, [fp, #-16]
-; CHECK: stur {{q[0-9]+}}, [fp, #-32]
+; CHECK: stur {{x[0-9]+}}, [x29, #-16]
+; CHECK: stur {{q[0-9]+}}, [x29, #-32]
; CHECK: str {{x[0-9]+}}, [sp, #48]
; CHECK: str {{q[0-9]+}}, [sp, #32]
-; Space for s1 is allocated at fp-32 = sp+64
+; Space for s1 is allocated at x29-32 = sp+64
; Space for s2 is allocated at sp+32
; CHECK: add x[[B:[0-9]+]], sp, #32
; CHECK: str x[[B]], [sp, #16]
-; CHECK: sub x[[A:[0-9]+]], fp, #32
+; CHECK: sub x[[A:[0-9]+]], x29, #32
; Address of s1 is passed on stack at sp+8
; CHECK: str x[[A]], [sp, #8]
; CHECK: movz w[[C:[0-9]+]], #9
@@ -336,8 +336,8 @@ entry:
; FAST: caller42_stack
; Space for s1 is allocated at fp-24
; Space for s2 is allocated at fp-48
-; FAST: sub x[[A:[0-9]+]], fp, #24
-; FAST: sub x[[B:[0-9]+]], fp, #48
+; FAST: sub x[[A:[0-9]+]], x29, #24
+; FAST: sub x[[B:[0-9]+]], x29, #48
; Call memcpy with size = 24 (0x18)
; FAST: orr {{x[0-9]+}}, xzr, #0x18
; FAST: str {{w[0-9]+}}, [sp]
@@ -399,7 +399,7 @@ entry:
; Space for s2 is allocated at sp
; FAST: caller43
-; FAST: mov fp, sp
+; FAST: mov x29, sp
; Space for s1 is allocated at sp+32
; Space for s2 is allocated at sp
; FAST: add x1, sp, #32
@@ -429,17 +429,17 @@ declare i32 @f43_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
define i32 @caller43_stack() #3 {
entry:
; CHECK: caller43_stack
-; CHECK: mov fp, sp
+; CHECK: mov x29, sp
; CHECK: sub sp, sp, #96
-; CHECK: stur {{q[0-9]+}}, [fp, #-16]
-; CHECK: stur {{q[0-9]+}}, [fp, #-32]
+; CHECK: stur {{q[0-9]+}}, [x29, #-16]
+; CHECK: stur {{q[0-9]+}}, [x29, #-32]
; CHECK: str {{q[0-9]+}}, [sp, #48]
; CHECK: str {{q[0-9]+}}, [sp, #32]
-; Space for s1 is allocated at fp-32 = sp+64
+; Space for s1 is allocated at x29-32 = sp+64
; Space for s2 is allocated at sp+32
; CHECK: add x[[B:[0-9]+]], sp, #32
; CHECK: str x[[B]], [sp, #16]
-; CHECK: sub x[[A:[0-9]+]], fp, #32
+; CHECK: sub x[[A:[0-9]+]], x29, #32
; Address of s1 is passed on stack at sp+8
; CHECK: str x[[A]], [sp, #8]
; CHECK: movz w[[C:[0-9]+]], #9
@@ -449,12 +449,12 @@ entry:
; FAST: sub sp, sp, #96
; Space for s1 is allocated at fp-32 = sp+64
; Space for s2 is allocated at sp+32
-; FAST: sub x[[A:[0-9]+]], fp, #32
+; FAST: sub x[[A:[0-9]+]], x29, #32
; FAST: add x[[B:[0-9]+]], sp, #32
-; FAST: stur {{x[0-9]+}}, [fp, #-32]
-; FAST: stur {{x[0-9]+}}, [fp, #-24]
-; FAST: stur {{x[0-9]+}}, [fp, #-16]
-; FAST: stur {{x[0-9]+}}, [fp, #-8]
+; FAST: stur {{x[0-9]+}}, [x29, #-32]
+; FAST: stur {{x[0-9]+}}, [x29, #-24]
+; FAST: stur {{x[0-9]+}}, [x29, #-16]
+; FAST: stur {{x[0-9]+}}, [x29, #-8]
; FAST: str {{x[0-9]+}}, [sp, #32]
; FAST: str {{x[0-9]+}}, [sp, #40]
; FAST: str {{x[0-9]+}}, [sp, #48]
@@ -487,6 +487,7 @@ entry:
; CHECK: str {{w[0-9]+}}, [sp, #16]
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp]
; FAST: i128_split
+; FAST: sub sp, sp, #48
; FAST: mov x[[ADDR:[0-9]+]], sp
; FAST: str {{w[0-9]+}}, [x[[ADDR]], #16]
; FAST: stp {{x[0-9]+}}, {{x[0-9]+}}, [x[[ADDR]]]
diff --git a/test/CodeGen/ARM64/arith.ll b/test/CodeGen/ARM64/arith.ll
index b6ff0da..7b65c9c 100644
--- a/test/CodeGen/ARM64/arith.ll
+++ b/test/CodeGen/ARM64/arith.ll
@@ -155,7 +155,7 @@ entry:
define i64 @t17(i16 %a, i64 %x) nounwind ssp {
entry:
; CHECK-LABEL: t17:
-; CHECK: sxth [[REG:x[0-9]+]], x0
+; CHECK: sbfm [[REG:x[0-9]+]], x0, #0, #15
; CHECK: sub x0, xzr, [[REG]], lsl #32
; CHECK: ret
%tmp16 = sext i16 %a to i64
diff --git a/test/CodeGen/ARM64/coalesce-ext.ll b/test/CodeGen/ARM64/coalesce-ext.ll
index 9e8d08e..090bbd9 100644
--- a/test/CodeGen/ARM64/coalesce-ext.ll
+++ b/test/CodeGen/ARM64/coalesce-ext.ll
@@ -7,7 +7,7 @@ define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
%D = trunc i64 %C to i32
%E = shl i64 %C, 32
%F = ashr i64 %E, 32
- ; CHECK: sxtw x[[EXT:[0-9]+]], x[[SUM]]
+ ; CHECK: sbfm x[[EXT:[0-9]+]], x[[SUM]], #0, #31
store volatile i64 %F, i64 *%P2
; CHECK: str x[[EXT]]
store volatile i32 %D, i32* %P
diff --git a/test/CodeGen/ARM64/fast-isel-alloca.ll b/test/CodeGen/ARM64/fast-isel-alloca.ll
index 8bbee16..1706e9e 100644
--- a/test/CodeGen/ARM64/fast-isel-alloca.ll
+++ b/test/CodeGen/ARM64/fast-isel-alloca.ll
@@ -14,6 +14,7 @@ entry:
define void @main() nounwind {
entry:
; CHECK: main
+; CHECK: mov x29, sp
; CHECK: mov x[[REG:[0-9]+]], sp
; CHECK-NEXT: orr x[[REG1:[0-9]+]], xzr, #0x8
; CHECK-NEXT: add x0, x[[REG]], x[[REG1]]
diff --git a/test/CodeGen/ARM64/fast-isel-call.ll b/test/CodeGen/ARM64/fast-isel-call.ll
index be0ca68..637ce28 100644
--- a/test/CodeGen/ARM64/fast-isel-call.ll
+++ b/test/CodeGen/ARM64/fast-isel-call.ll
@@ -24,8 +24,8 @@ entry:
define i32 @foo1(i32 %a) nounwind {
entry:
; CHECK: foo1
-; CHECK: stur w0, [fp, #-4]
-; CHECK-NEXT: ldur w0, [fp, #-4]
+; CHECK: stur w0, [x29, #-4]
+; CHECK-NEXT: ldur w0, [x29, #-4]
; CHECK-NEXT: bl _call1
%a.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
diff --git a/test/CodeGen/ARM64/fast-isel-conversion.ll b/test/CodeGen/ARM64/fast-isel-conversion.ll
index 4e62e33..3b8984e 100644
--- a/test/CodeGen/ARM64/fast-isel-conversion.ll
+++ b/test/CodeGen/ARM64/fast-isel-conversion.ll
@@ -57,7 +57,7 @@ entry:
; CHECK: uxth w0, w0
; CHECK: str w0, [sp, #8]
; CHECK: ldr w0, [sp, #8]
-; CHECK: uxtw x3, w0
+; CHECK: ubfm x3, w0, #0, #31
; CHECK: str x3, [sp]
; CHECK: ldr x0, [sp], #16
; CHECK: ret
@@ -113,7 +113,7 @@ entry:
; CHECK: sxth w0, w0
; CHECK: str w0, [sp, #8]
; CHECK: ldr w0, [sp, #8]
-; CHECK: sxtw x3, w0
+; CHECK: sbfm x3, w0, #0, #31
; CHECK: str x3, [sp]
; CHECK: ldr x0, [sp], #16
; CHECK: ret
@@ -142,7 +142,7 @@ entry:
define i64 @sext_2(i8 signext %a) nounwind ssp {
entry:
; CHECK: sext_2
-; CHECK: sxtb x0, w0
+; CHECK: sbfm x0, w0, #0, #7
%conv = sext i8 %a to i64
ret i64 %conv
}
diff --git a/test/CodeGen/ARM64/frameaddr.ll b/test/CodeGen/ARM64/frameaddr.ll
index d0635ad..469078c 100644
--- a/test/CodeGen/ARM64/frameaddr.ll
+++ b/test/CodeGen/ARM64/frameaddr.ll
@@ -3,10 +3,10 @@
define i8* @t() nounwind {
entry:
; CHECK-LABEL: t:
-; CHECK: stp fp, lr, [sp, #-16]!
-; CHECK: mov fp, sp
-; CHECK: mov x0, fp
-; CHECK: ldp fp, lr, [sp], #16
+; CHECK: stp x29, x30, [sp, #-16]!
+; CHECK: mov x29, sp
+; CHECK: mov x0, x29
+; CHECK: ldp x29, x30, [sp], #16
; CHECK: ret
%0 = call i8* @llvm.frameaddress(i32 0)
ret i8* %0
diff --git a/test/CodeGen/ARM64/hello.ll b/test/CodeGen/ARM64/hello.ll
index f870fff..a6346fb 100644
--- a/test/CodeGen/ARM64/hello.ll
+++ b/test/CodeGen/ARM64/hello.ll
@@ -2,27 +2,27 @@
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix=CHECK-LINUX
; CHECK-LABEL: main:
-; CHECK: stp fp, lr, [sp, #-16]!
-; CHECK-NEXT: mov fp, sp
+; CHECK: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16
-; CHECK-NEXT: stur wzr, [fp, #-4]
+; CHECK-NEXT: stur wzr, [x29, #-4]
; CHECK: adrp x0, L_.str at PAGE
; CHECK: add x0, x0, L_.str at PAGEOFF
; CHECK-NEXT: bl _puts
-; CHECK-NEXT: mov sp, fp
-; CHECK-NEXT: ldp fp, lr, [sp], #16
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16
; CHECK-NEXT: ret
; CHECK-LINUX-LABEL: main:
-; CHECK-LINUX: stp fp, lr, [sp, #-16]!
-; CHECK-LINUX-NEXT: mov fp, sp
+; CHECK-LINUX: stp x29, x30, [sp, #-16]!
+; CHECK-LINUX-NEXT: mov x29, sp
; CHECK-LINUX-NEXT: sub sp, sp, #16
-; CHECK-LINUX-NEXT: stur wzr, [fp, #-4]
+; CHECK-LINUX-NEXT: stur wzr, [x29, #-4]
; CHECK-LINUX: adrp x0, .L.str
; CHECK-LINUX: add x0, x0, :lo12:.L.str
; CHECK-LINUX-NEXT: bl puts
-; CHECK-LINUX-NEXT: mov sp, fp
-; CHECK-LINUX-NEXT: ldp fp, lr, [sp], #16
+; CHECK-LINUX-NEXT: mov sp, x29
+; CHECK-LINUX-NEXT: ldp x29, x30, [sp], #16
; CHECK-LINUX-NEXT: ret
@.str = private unnamed_addr constant [7 x i8] c"hello\0A\00"
diff --git a/test/CodeGen/ARM64/patchpoint.ll b/test/CodeGen/ARM64/patchpoint.ll
index 993e3eb..c9f63d9 100644
--- a/test/CodeGen/ARM64/patchpoint.ll
+++ b/test/CodeGen/ARM64/patchpoint.ll
@@ -25,10 +25,10 @@ entry:
; as a leaf function.
;
; CHECK-LABEL: caller_meta_leaf
-; CHECK: mov fp, sp
+; CHECK: mov x29, sp
; CHECK-NEXT: sub sp, sp, #32
; CHECK: Ltmp
-; CHECK: mov sp, fp
+; CHECK: mov sp, x29
; CHECK: ret
define void @caller_meta_leaf() {
diff --git a/test/CodeGen/ARM64/returnaddr.ll b/test/CodeGen/ARM64/returnaddr.ll
index e06ce90..285b295 100644
--- a/test/CodeGen/ARM64/returnaddr.ll
+++ b/test/CodeGen/ARM64/returnaddr.ll
@@ -3,7 +3,7 @@
define i8* @rt0(i32 %x) nounwind readnone {
entry:
; CHECK-LABEL: rt0:
-; CHECK: mov x0, lr
+; CHECK: mov x0, x30
; CHECK: ret
%0 = tail call i8* @llvm.returnaddress(i32 0)
ret i8* %0
@@ -12,12 +12,12 @@ entry:
define i8* @rt2() nounwind readnone {
entry:
; CHECK-LABEL: rt2:
-; CHECK: stp fp, lr, [sp, #-16]!
-; CHECK: mov fp, sp
-; CHECK: ldr x[[REG:[0-9]+]], [fp]
+; CHECK: stp x29, x30, [sp, #-16]!
+; CHECK: mov x29, sp
+; CHECK: ldr x[[REG:[0-9]+]], [x29]
; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]]]
; CHECK: ldr x0, [x[[REG2]], #8]
-; CHECK: ldp fp, lr, [sp], #16
+; CHECK: ldp x29, x30, [sp], #16
; CHECK: ret
%0 = tail call i8* @llvm.returnaddress(i32 2)
ret i8* %0
diff --git a/test/CodeGen/ARM64/shifted-sext.ll b/test/CodeGen/ARM64/shifted-sext.ll
index e553be5..7f17f6b 100644
--- a/test/CodeGen/ARM64/shifted-sext.ll
+++ b/test/CodeGen/ARM64/shifted-sext.ll
@@ -133,7 +133,7 @@ define i64 @extendedRightShiftcharToint64By8(i8 signext %a) nounwind readnone ss
entry:
; CHECK-LABEL: extendedRightShiftcharToint64By8:
; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sxtb x[[REG]], x[[REG]]
+; CHECK: sbfm x[[REG]], x[[REG]], #0, #7
; CHECK: asr x0, x[[REG]], #8
%inc = add i8 %a, 1
%conv = sext i8 %inc to i64
@@ -223,7 +223,7 @@ define i64 @extendedRightShiftshortToint64By16(i16 signext %a) nounwind readnone
entry:
; CHECK-LABEL: extendedRightShiftshortToint64By16:
; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sxth x[[REG]], x[[REG]]
+; CHECK: sbfm x[[REG]], x[[REG]], #0, #15
; CHECK: asr x0, x[[REG]], #16
%inc = add i16 %a, 1
%conv = sext i16 %inc to i64
@@ -268,7 +268,7 @@ define i64 @extendedRightShiftintToint64By32(i32 %a) nounwind readnone ssp {
entry:
; CHECK-LABEL: extendedRightShiftintToint64By32:
; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sxtw x[[REG]], x[[REG]]
+; CHECK: sbfm x[[REG]], x[[REG]], #0, #31
; CHECK: asr x0, x[[REG]], #32
%inc = add nsw i32 %a, 1
%conv = sext i32 %inc to i64
diff --git a/test/MC/ARM64/adr.s b/test/MC/ARM64/adr.s
new file mode 100644
index 0000000..3442225
--- /dev/null
+++ b/test/MC/ARM64/adr.s
@@ -0,0 +1,31 @@
+// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+adr x0, #0
+adr x0, #1
+adr x0, 1f
+adr x0, foo
+// CHECK: adr x0, #0 // encoding: [0x00,0x00,0x00,0x10]
+// CHECK: adr x0, #1 // encoding: [0x00,0x00,0x00,0x30]
+// CHECK: adr x0, .Ltmp0 // encoding: [A,A,A,0x10'A']
+// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm64_pcrel_adr_imm21
+// CHECK: adr x0, foo // encoding: [A,A,A,0x10'A']
+// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_arm64_pcrel_adr_imm21
+
+adrp x0, #0
+adrp x0, #4096
+adrp x0, 1f
+adrp x0, foo
+// CHECK: adrp x0, #0 // encoding: [0x00,0x00,0x00,0x90]
+// CHECK: adrp x0, #4096 // encoding: [0x00,0x00,0x00,0xb0]
+// CHECK: adrp x0, .Ltmp0 // encoding: [A,A,A,0x90'A']
+// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm64_pcrel_adrp_imm21
+// CHECK: adrp x0, foo // encoding: [A,A,A,0x90'A']
+// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_arm64_pcrel_adrp_imm21
+
+adr x0, #0xffffffff
+adrp x0, #0xffffffff
+adrp x0, #1
+// CHECK-ERRORS: error: expected label or encodable integer pc offset
+// CHECK-ERRORS: error: expected label or encodable integer pc offset
+// CHECK-ERRORS: error: expected label or encodable integer pc offset
diff --git a/test/MC/ARM64/aliases.s b/test/MC/ARM64/aliases.s
index 055edb5..13a1716 100644
--- a/test/MC/ARM64/aliases.s
+++ b/test/MC/ARM64/aliases.s
@@ -103,7 +103,7 @@ foo:
; CHECK: cmp wzr, w1 ; encoding: [0xff,0x03,0x01,0x6b]
; CHECK: cmp x8, w8, uxtw ; encoding: [0x1f,0x41,0x28,0xeb]
; CHECK: cmp w9, w8, uxtw ; encoding: [0x3f,0x41,0x28,0x6b]
-; CHECK: cmp wsp, w9 ; encoding: [0xff,0x63,0x29,0x6b]
+; CHECK: cmp wsp, w9 ; encoding: [0xff,0x43,0x29,0x6b]
;-----------------------------------------------------------------------------
@@ -139,9 +139,13 @@ foo:
mov w0, #0xffffffff
mov w0, #0xffffff00
+ mov wzr, #0xffffffff
+ mov wzr, #0xffffff00
; CHECK: movn w0, #0
; CHECK: movn w0, #255
+; CHECK: movn wzr, #0
+; CHECK: movn wzr, #255
;-----------------------------------------------------------------------------
; MVN aliases
@@ -155,6 +159,14 @@ foo:
; CHECK: mvn x2, x3 ; encoding: [0xe2,0x03,0x23,0xaa]
; CHECK: mvn w4, w9 ; encoding: [0xe4,0x03,0x29,0x2a]
+ mvn w4, w9, lsl #1
+ mvn x2, x3, lsl #1
+ orn w4, wzr, w9, lsl #1
+
+; CHECK: mvn w4, w9, lsl #1 ; encoding: [0xe4,0x07,0x29,0x2a]
+; CHECK: mvn x2, x3, lsl #1 ; encoding: [0xe2,0x07,0x23,0xaa]
+; CHECK: mvn w4, w9, lsl #1 ; encoding: [0xe4,0x07,0x29,0x2a]
+
;-----------------------------------------------------------------------------
; Bitfield aliases
;-----------------------------------------------------------------------------
@@ -227,20 +239,6 @@ foo:
; CHECK: uxtb w1, w2
; CHECK: uxth w1, w2
- sxtb x1, x2
- sxth x1, x2
- sxtw x1, x2
- uxtb x1, x2
- uxth x1, x2
- uxtw x1, x2
-
-; CHECK: sxtb x1, x2
-; CHECK: sxth x1, x2
-; CHECK: sxtw x1, x2
-; CHECK: uxtb x1, x2
-; CHECK: uxth x1, x2
-; CHECK: uxtw x1, x2
-
;-----------------------------------------------------------------------------
; Negate with carry
;-----------------------------------------------------------------------------
@@ -408,120 +406,128 @@ foo:
; CHECK: tlbi ipas2e1
sys #4, c8, c4, #5
; CHECK: tlbi ipas2le1
+ sys #4, c8, c0, #1
+; CHECK: tlbi ipas2e1is
+ sys #4, c8, c0, #5
+; CHECK: tlbi ipas2le1is
sys #4, c8, c7, #6
; CHECK: tlbi vmalls12e1
sys #4, c8, c3, #6
; CHECK: tlbi vmalls12e1is
ic ialluis
-; CHECK: ic ialluis
+; CHECK: ic ialluis ; encoding: [0x1f,0x71,0x08,0xd5]
ic iallu
-; CHECK: ic iallu
- ic ivau
-; CHECK: ic ivau
-
- dc zva
-; CHECK: dc zva
- dc ivac
-; CHECK: dc ivac
- dc isw
-; CHECK: dc isw
- dc cvac
-; CHECK: dc cvac
- dc csw
-; CHECK: dc csw
- dc cvau
-; CHECK: dc cvau
- dc civac
-; CHECK: dc civac
- dc cisw
-; CHECK: dc cisw
-
- at s1e1r
-; CHECK: at s1e1r
- at s1e2r
-; CHECK: at s1e2r
- at s1e3r
-; CHECK: at s1e3r
- at s1e1w
-; CHECK: at s1e1w
- at s1e2w
-; CHECK: at s1e2w
- at s1e3w
-; CHECK: at s1e3w
- at s1e0r
-; CHECK: at s1e0r
- at s1e0w
-; CHECK: at s1e0w
- at s12e1r
-; CHECK: at s12e1r
- at s12e1w
-; CHECK: at s12e1w
- at s12e0r
-; CHECK: at s12e0r
- at s12e0w
-; CHECK: at s12e0w
+; CHECK: ic iallu ; encoding: [0x1f,0x75,0x08,0xd5]
+ ic ivau, x0
+; CHECK: ic ivau, x0 ; encoding: [0x20,0x75,0x0b,0xd5]
+
+ dc zva, x0
+; CHECK: dc zva, x0 ; encoding: [0x20,0x74,0x0b,0xd5]
+ dc ivac, x0
+; CHECK: dc ivac, x0 ; encoding: [0x20,0x76,0x08,0xd5]
+ dc isw, x0
+; CHECK: dc isw, x0 ; encoding: [0x40,0x76,0x08,0xd5]
+ dc cvac, x0
+; CHECK: dc cvac, x0 ; encoding: [0x20,0x7a,0x0b,0xd5]
+ dc csw, x0
+; CHECK: dc csw, x0 ; encoding: [0x40,0x7a,0x08,0xd5]
+ dc cvau, x0
+; CHECK: dc cvau, x0 ; encoding: [0x20,0x7b,0x0b,0xd5]
+ dc civac, x0
+; CHECK: dc civac, x0 ; encoding: [0x20,0x7e,0x0b,0xd5]
+ dc cisw, x0
+; CHECK: dc cisw, x0 ; encoding: [0x40,0x7e,0x08,0xd5]
+
+ at s1e1r, x0
+; CHECK: at s1e1r, x0 ; encoding: [0x00,0x78,0x08,0xd5]
+ at s1e2r, x0
+; CHECK: at s1e2r, x0 ; encoding: [0x00,0x78,0x0c,0xd5]
+ at s1e3r, x0
+; CHECK: at s1e3r, x0 ; encoding: [0x00,0x78,0x0e,0xd5]
+ at s1e1w, x0
+; CHECK: at s1e1w, x0 ; encoding: [0x20,0x78,0x08,0xd5]
+ at s1e2w, x0
+; CHECK: at s1e2w, x0 ; encoding: [0x20,0x78,0x0c,0xd5]
+ at s1e3w, x0
+; CHECK: at s1e3w, x0 ; encoding: [0x20,0x78,0x0e,0xd5]
+ at s1e0r, x0
+; CHECK: at s1e0r, x0 ; encoding: [0x40,0x78,0x08,0xd5]
+ at s1e0w, x0
+; CHECK: at s1e0w, x0 ; encoding: [0x60,0x78,0x08,0xd5]
+ at s12e1r, x0
+; CHECK: at s12e1r, x0 ; encoding: [0x80,0x78,0x0c,0xd5]
+ at s12e1w, x0
+; CHECK: at s12e1w, x0 ; encoding: [0xa0,0x78,0x0c,0xd5]
+ at s12e0r, x0
+; CHECK: at s12e0r, x0 ; encoding: [0xc0,0x78,0x0c,0xd5]
+ at s12e0w, x0
+; CHECK: at s12e0w, x0 ; encoding: [0xe0,0x78,0x0c,0xd5]
tlbi vmalle1is
-; CHECK: tlbi vmalle1is
+; CHECK: tlbi vmalle1is ; encoding: [0x1f,0x83,0x08,0xd5]
tlbi alle2is
-; CHECK: tlbi alle2is
+; CHECK: tlbi alle2is ; encoding: [0x1f,0x83,0x0c,0xd5]
tlbi alle3is
-; CHECK: tlbi alle3is
- tlbi vae1is
-; CHECK: tlbi vae1is
- tlbi vae2is
-; CHECK: tlbi vae2is
- tlbi vae3is
-; CHECK: tlbi vae3is
- tlbi aside1is
-; CHECK: tlbi aside1is
- tlbi vaae1is
-; CHECK: tlbi vaae1is
+; CHECK: tlbi alle3is ; encoding: [0x1f,0x83,0x0e,0xd5]
+ tlbi vae1is, x0
+; CHECK: tlbi vae1is, x0 ; encoding: [0x20,0x83,0x08,0xd5]
+ tlbi vae2is, x0
+; CHECK: tlbi vae2is, x0 ; encoding: [0x20,0x83,0x0c,0xd5]
+ tlbi vae3is, x0
+; CHECK: tlbi vae3is, x0 ; encoding: [0x20,0x83,0x0e,0xd5]
+ tlbi aside1is, x0
+; CHECK: tlbi aside1is, x0 ; encoding: [0x40,0x83,0x08,0xd5]
+ tlbi vaae1is, x0
+; CHECK: tlbi vaae1is, x0 ; encoding: [0x60,0x83,0x08,0xd5]
tlbi alle1is
-; CHECK: tlbi alle1is
- tlbi vale1is
-; CHECK: tlbi vale1is
- tlbi vaale1is
-; CHECK: tlbi vaale1is
+; CHECK: tlbi alle1is ; encoding: [0x9f,0x83,0x0c,0xd5]
+ tlbi vale1is, x0
+; CHECK: tlbi vale1is, x0 ; encoding: [0xa0,0x83,0x08,0xd5]
+ tlbi vaale1is, x0
+; CHECK: tlbi vaale1is, x0 ; encoding: [0xe0,0x83,0x08,0xd5]
tlbi vmalle1
-; CHECK: tlbi vmalle1
+; CHECK: tlbi vmalle1 ; encoding: [0x1f,0x87,0x08,0xd5]
tlbi alle2
-; CHECK: tlbi alle2
- tlbi vale2is
-; CHECK: tlbi vale2is
- tlbi vale3is
-; CHECK: tlbi vale3is
+; CHECK: tlbi alle2 ; encoding: [0x1f,0x87,0x0c,0xd5]
+ tlbi vale2is, x0
+; CHECK: tlbi vale2is, x0 ; encoding: [0xa0,0x83,0x0c,0xd5]
+ tlbi vale3is, x0
+; CHECK: tlbi vale3is, x0 ; encoding: [0xa0,0x83,0x0e,0xd5]
tlbi alle3
-; CHECK: tlbi alle3
- tlbi vae1
-; CHECK: tlbi vae1
- tlbi vae2
-; CHECK: tlbi vae2
- tlbi vae3
-; CHECK: tlbi vae3
- tlbi aside1
-; CHECK: tlbi aside1
- tlbi vaae1
-; CHECK: tlbi vaae1
+; CHECK: tlbi alle3 ; encoding: [0x1f,0x87,0x0e,0xd5]
+ tlbi vae1, x0
+; CHECK: tlbi vae1, x0 ; encoding: [0x20,0x87,0x08,0xd5]
+ tlbi vae2, x0
+; CHECK: tlbi vae2, x0 ; encoding: [0x20,0x87,0x0c,0xd5]
+ tlbi vae3, x0
+; CHECK: tlbi vae3, x0 ; encoding: [0x20,0x87,0x0e,0xd5]
+ tlbi aside1, x0
+; CHECK: tlbi aside1, x0 ; encoding: [0x40,0x87,0x08,0xd5]
+ tlbi vaae1, x0
+; CHECK: tlbi vaae1, x0 ; encoding: [0x60,0x87,0x08,0xd5]
tlbi alle1
-; CHECK: tlbi alle1
- tlbi vale1
-; CHECK: tlbi vale1
- tlbi vale2
-; CHECK: tlbi vale2
- tlbi vale3
-; CHECK: tlbi vale3
- tlbi vaale1
-; CHECK: tlbi vaale1
- tlbi ipas2e1, x10
-; CHECK: tlbi ipas2e1, x10
- tlbi ipas2le1, x1
-; CHECK: tlbi ipas2le1, x1
+; CHECK: tlbi alle1 ; encoding: [0x9f,0x87,0x0c,0xd5
+ tlbi vale1, x0
+; CHECK: tlbi vale1, x0 ; encoding: [0xa0,0x87,0x08,0xd5]
+ tlbi vale2, x0
+; CHECK: tlbi vale2, x0 ; encoding: [0xa0,0x87,0x0c,0xd5]
+ tlbi vale3, x0
+; CHECK: tlbi vale3, x0 ; encoding: [0xa0,0x87,0x0e,0xd5]
+ tlbi vaale1, x0
+; CHECK: tlbi vaale1, x0 ; encoding: [0xe0,0x87,0x08,0xd5]
+ tlbi ipas2e1, x0
+; CHECK: tlbi ipas2e1, x0 ; encoding: [0x20,0x84,0x0c,0xd5]
+ tlbi ipas2le1, x0
+; CHECK: tlbi ipas2le1, x0 ; encoding: [0xa0,0x84,0x0c,0xd5]
+ tlbi ipas2e1is, x0
+; CHECK: tlbi ipas2e1is, x0 ; encoding: [0x20,0x80,0x0c,0xd5]
+ tlbi ipas2le1is, x0
+; CHECK: tlbi ipas2le1is, x0 ; encoding: [0xa0,0x80,0x0c,0xd5]
tlbi vmalls12e1
-; CHECK: tlbi vmalls12e1
+; CHECK: tlbi vmalls12e1 ; encoding: [0xdf,0x87,0x0c,0xd5]
tlbi vmalls12e1is
-; CHECK: tlbi vmalls12e1is
+; CHECK: tlbi vmalls12e1is ; encoding: [0xdf,0x83,0x0c,0xd5]
;-----------------------------------------------------------------------------
; 5.8.5 Vector Arithmetic aliases
diff --git a/test/MC/ARM64/arithmetic-encoding.s b/test/MC/ARM64/arithmetic-encoding.s
index 7c89244..6d28bce 100644
--- a/test/MC/ARM64/arithmetic-encoding.s
+++ b/test/MC/ARM64/arithmetic-encoding.s
@@ -223,7 +223,7 @@ foo:
; CHECK: add w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x0b]
; CHECK: add w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x0b]
-; CHECK: add w2, wsp, w3, lsl #1 ; encoding: [0xe2,0x67,0x23,0x0b]
+; CHECK: add w2, wsp, w3, lsl #1 ; encoding: [0xe2,0x47,0x23,0x0b]
; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b]
; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b]
@@ -313,7 +313,7 @@ foo:
; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b]
; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b]
-; CHECK: adds wzr, wsp, w3, lsl #4 ; encoding: [0xff,0x73,0x23,0x2b]
+; CHECK: adds wzr, wsp, w3, lsl #4 ; encoding: [0xff,0x53,0x23,0x2b]
subs w1, w2, w3, uxtb
subs w1, w2, w3, uxth
@@ -364,12 +364,12 @@ foo:
cmp sp, w8, uxtw
subs xzr, sp, w8, uxtw
-; CHECK: cmp wsp, w9 ; encoding: [0xff,0x63,0x29,0x6b]
+; CHECK: cmp wsp, w9 ; encoding: [0xff,0x43,0x29,0x6b]
; CHECK: subs x3, sp, x9, lsl #2 ; encoding: [0xe3,0x6b,0x29,0xeb]
; CHECK: cmp wsp, w8 ; encoding: [0xff,0x43,0x28,0x6b]
; CHECK: cmp wsp, w8 ; encoding: [0xff,0x43,0x28,0x6b]
-; CHECK: cmp sp, w8 ; encoding: [0xff,0x43,0x28,0xeb]
-; CHECK: cmp sp, w8 ; encoding: [0xff,0x43,0x28,0xeb]
+; CHECK: cmp sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xeb]
+; CHECK: cmp sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xeb]
sub wsp, w9, w8, uxtw
sub w1, wsp, w8, uxtw
@@ -383,11 +383,11 @@ foo:
; CHECK: sub wsp, w9, w8 ; encoding: [0x3f,0x41,0x28,0x4b]
; CHECK: sub w1, wsp, w8 ; encoding: [0xe1,0x43,0x28,0x4b]
; CHECK: sub wsp, wsp, w8 ; encoding: [0xff,0x43,0x28,0x4b]
-; CHECK: sub sp, x9, w8 ; encoding: [0x3f,0x41,0x28,0xcb]
-; CHECK: sub x1, sp, w8 ; encoding: [0xe1,0x43,0x28,0xcb]
-; CHECK: sub sp, sp, w8 ; encoding: [0xff,0x43,0x28,0xcb]
+; CHECK: sub sp, x9, w8, uxtw ; encoding: [0x3f,0x41,0x28,0xcb]
+; CHECK: sub x1, sp, w8, uxtw ; encoding: [0xe1,0x43,0x28,0xcb]
+; CHECK: sub sp, sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xcb]
; CHECK: subs w1, wsp, w8 ; encoding: [0xe1,0x43,0x28,0x6b]
-; CHECK: subs x1, sp, w8 ; encoding: [0xe1,0x43,0x28,0xeb]
+; CHECK: subs x1, sp, w8, uxtw ; encoding: [0xe1,0x43,0x28,0xeb]
;==---------------------------------------------------------------------------==
; Signed/Unsigned divide
diff --git a/test/MC/ARM64/bitfield-encoding.s b/test/MC/ARM64/bitfield-encoding.s
index cdbac08..a40906f 100644
--- a/test/MC/ARM64/bitfield-encoding.s
+++ b/test/MC/ARM64/bitfield-encoding.s
@@ -11,6 +11,10 @@ foo:
sbfm x1, x2, #1, #15
ubfm w1, w2, #1, #15
ubfm x1, x2, #1, #15
+ sbfiz wzr, w0, #31, #1
+ sbfiz xzr, x0, #31, #1
+ ubfiz wzr, w0, #31, #1
+ ubfiz xzr, x0, #31, #1
; CHECK: bfm w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x33]
; CHECK: bfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xb3]
@@ -18,6 +22,10 @@ foo:
; CHECK: sbfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0x93]
; CHECK: ubfm w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x53]
; CHECK: ubfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xd3]
+; CHECK: sbfm wzr, w0, #1, #0 ; encoding: [0x1f,0x00,0x01,0x13]
+; CHECK: sbfm xzr, x0, #33, #0 ; encoding: [0x1f,0x00,0x61,0x93]
+; CHECK: lsl wzr, w0, #31 ; encoding: [0x1f,0x00,0x01,0x53]
+; CHECK: ubfm xzr, x0, #33, #0 ; encoding: [0x1f,0x00,0x61,0xd3]
;==---------------------------------------------------------------------------==
; 5.4.5 Extract (immediate)
diff --git a/test/MC/ARM64/branch-encoding.s b/test/MC/ARM64/branch-encoding.s
index 7857fea..4574047 100644
--- a/test/MC/ARM64/branch-encoding.s
+++ b/test/MC/ARM64/branch-encoding.s
@@ -72,7 +72,7 @@ foo:
; CHECK: b.le L1 ; encoding: [0bAAA01101,A,A,0x54]
; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
b.al L1
-; CHECK: b L1 ; encoding: [0bAAA01110,A,A,0x54]
+; CHECK: b.al L1 ; encoding: [0bAAA01110,A,A,0x54]
; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
L1:
b #28
diff --git a/test/MC/ARM64/diags.s b/test/MC/ARM64/diags.s
index d857fe1..e82147e 100644
--- a/test/MC/ARM64/diags.s
+++ b/test/MC/ARM64/diags.s
@@ -240,3 +240,103 @@ b.c #0x4
; CHECK-ERRORS: error: invalid condition code
; CHECK-ERRORS: b.c #0x4
; CHECK-ERRORS: ^
+
+ic ialluis, x0
+; CHECK-ERRORS: error: specified ic op does not use a register
+ic iallu, x0
+; CHECK-ERRORS: error: specified ic op does not use a register
+ic ivau
+; CHECK-ERRORS: error: specified ic op requires a register
+
+dc zva
+; CHECK-ERRORS: error: specified dc op requires a register
+dc ivac
+; CHECK-ERRORS: error: specified dc op requires a register
+dc isw
+; CHECK-ERRORS: error: specified dc op requires a register
+dc cvac
+; CHECK-ERRORS: error: specified dc op requires a register
+dc csw
+; CHECK-ERRORS: error: specified dc op requires a register
+dc cvau
+; CHECK-ERRORS: error: specified dc op requires a register
+dc civac
+; CHECK-ERRORS: error: specified dc op requires a register
+dc cisw
+; CHECK-ERRORS: error: specified dc op requires a register
+
+at s1e1r
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e2r
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e3r
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e1w
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e2w
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e3w
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e0r
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e0w
+; CHECK-ERRORS: error: specified at op requires a register
+at s12e1r
+; CHECK-ERRORS: error: specified at op requires a register
+at s12e1w
+; CHECK-ERRORS: error: specified at op requires a register
+at s12e0r
+; CHECK-ERRORS: error: specified at op requires a register
+at s12e0w
+; CHECK-ERRORS: error: specified at op requires a register
+
+tlbi vmalle1is, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi vmalle1, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle1is, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle2is, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle3is, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle1, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle2, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle3, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi vae1is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vae2is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vae3is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi aside1is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vaae1is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale1is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vaale1is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale2is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale3is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vae1
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vae2
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vae3
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi aside1
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vaae1
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale1
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale2
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale3
+; CHECK-ERRORS: error: specified tlbi op requires a register
diff --git a/test/MC/ARM64/elf-relocs.s b/test/MC/ARM64/elf-relocs.s
index 31446ff..7eec085 100644
--- a/test/MC/ARM64/elf-relocs.s
+++ b/test/MC/ARM64/elf-relocs.s
@@ -14,7 +14,7 @@
// CHECK-OBJ: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
add x20, x30, #:tprel_lo12:sym
-// CHECK: add x20, lr, :tprel_lo12:sym
+// CHECK: add x20, x30, :tprel_lo12:sym
// CHECK-OBJ: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
add x9, x12, #:tprel_lo12_nc:sym
@@ -38,7 +38,7 @@
// CHECK-OBJ:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
add x20, x30, #:tprel_lo12:sym+12
-// CHECK: add x20, lr, :tprel_lo12:sym+12
+// CHECK: add x20, x30, :tprel_lo12:sym+12
// CHECK-OBJ: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
add x9, x12, #:tprel_lo12_nc:sym+54
@@ -72,7 +72,7 @@
// CHECK-OBJ: 50 R_AARCH64_ADR_GOT_PAGE sym
adrp x29, :gottprel:sym
-// CHECK: adrp fp, :gottprel:sym
+// CHECK: adrp x29, :gottprel:sym
// CHECK-OBJ: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
adrp x2, :tlsdesc:sym
@@ -105,7 +105,7 @@ trickQuestion:
ldrsb w23, [x19, #:dtprel_lo12:sym]
ldrsb x17, [x13, #:dtprel_lo12_nc:sym]
ldr b11, [x7, #:dtprel_lo12:sym]
-// CHECK: ldrb w23, [fp, :dtprel_lo12_nc:sym]
+// CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
@@ -144,7 +144,7 @@ trickQuestion:
ldrsh w23, [x19, #:dtprel_lo12:sym]
ldrsh x17, [x13, #:dtprel_lo12_nc:sym]
ldr h11, [x7, #:dtprel_lo12:sym]
-// CHECK: ldrh w23, [fp, :dtprel_lo12_nc:sym]
+// CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
diff --git a/test/MC/ARM64/fp-encoding.s b/test/MC/ARM64/fp-encoding.s
index 25474c1..7c7208f 100644
--- a/test/MC/ARM64/fp-encoding.s
+++ b/test/MC/ARM64/fp-encoding.s
@@ -1,4 +1,4 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding -output-asm-variant=1 < %s | FileCheck %s
foo:
;-----------------------------------------------------------------------------
@@ -158,148 +158,84 @@ foo:
; CHECK: fcvt h1, s2 ; encoding: [0x41,0xc0,0x23,0x1e]
fcvtas w1, d2
- fcvtas w1, d2, #1
fcvtas x1, d2
- fcvtas x1, d2, #1
fcvtas w1, s2
- fcvtas w1, s2, #1
fcvtas x1, s2
- fcvtas x1, s2, #1
; CHECK: fcvtas w1, d2 ; encoding: [0x41,0x00,0x64,0x1e]
-; CHECK: fcvtas w1, d2, #1 ; encoding: [0x41,0xfc,0x44,0x1e]
; CHECK: fcvtas x1, d2 ; encoding: [0x41,0x00,0x64,0x9e]
-; CHECK: fcvtas x1, d2, #1 ; encoding: [0x41,0xfc,0x44,0x9e]
; CHECK: fcvtas w1, s2 ; encoding: [0x41,0x00,0x24,0x1e]
-; CHECK: fcvtas w1, s2, #1 ; encoding: [0x41,0xfc,0x04,0x1e]
; CHECK: fcvtas x1, s2 ; encoding: [0x41,0x00,0x24,0x9e]
-; CHECK: fcvtas x1, s2, #1 ; encoding: [0x41,0xfc,0x04,0x9e]
fcvtau w1, s2
- fcvtau w1, s2, #1
fcvtau w1, d2
- fcvtau w1, d2, #1
fcvtau x1, s2
- fcvtau x1, s2, #1
fcvtau x1, d2
- fcvtau x1, d2, #1
; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e]
-; CHECK: fcvtau w1, s2, #1 ; encoding: [0x41,0xfc,0x05,0x1e]
; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e]
-; CHECK: fcvtau w1, d2, #1 ; encoding: [0x41,0xfc,0x45,0x1e]
; CHECK: fcvtau x1, s2 ; encoding: [0x41,0x00,0x25,0x9e]
-; CHECK: fcvtau x1, s2, #1 ; encoding: [0x41,0xfc,0x05,0x9e]
; CHECK: fcvtau x1, d2 ; encoding: [0x41,0x00,0x65,0x9e]
-; CHECK: fcvtau x1, d2, #1 ; encoding: [0x41,0xfc,0x45,0x9e]
fcvtms w1, s2
- fcvtms w1, s2, #1
fcvtms w1, d2
- fcvtms w1, d2, #1
fcvtms x1, s2
- fcvtms x1, s2, #1
fcvtms x1, d2
- fcvtms x1, d2, #1
; CHECK: fcvtms w1, s2 ; encoding: [0x41,0x00,0x30,0x1e]
-; CHECK: fcvtms w1, s2, #1 ; encoding: [0x41,0xfc,0x10,0x1e]
; CHECK: fcvtms w1, d2 ; encoding: [0x41,0x00,0x70,0x1e]
-; CHECK: fcvtms w1, d2, #1 ; encoding: [0x41,0xfc,0x50,0x1e]
; CHECK: fcvtms x1, s2 ; encoding: [0x41,0x00,0x30,0x9e]
-; CHECK: fcvtms x1, s2, #1 ; encoding: [0x41,0xfc,0x10,0x9e]
; CHECK: fcvtms x1, d2 ; encoding: [0x41,0x00,0x70,0x9e]
-; CHECK: fcvtms x1, d2, #1 ; encoding: [0x41,0xfc,0x50,0x9e]
fcvtmu w1, s2
- fcvtmu w1, s2, #1
fcvtmu w1, d2
- fcvtmu w1, d2, #1
fcvtmu x1, s2
- fcvtmu x1, s2, #1
fcvtmu x1, d2
- fcvtmu x1, d2, #1
; CHECK: fcvtmu w1, s2 ; encoding: [0x41,0x00,0x31,0x1e]
-; CHECK: fcvtmu w1, s2, #1 ; encoding: [0x41,0xfc,0x11,0x1e]
; CHECK: fcvtmu w1, d2 ; encoding: [0x41,0x00,0x71,0x1e]
-; CHECK: fcvtmu w1, d2, #1 ; encoding: [0x41,0xfc,0x51,0x1e]
; CHECK: fcvtmu x1, s2 ; encoding: [0x41,0x00,0x31,0x9e]
-; CHECK: fcvtmu x1, s2, #1 ; encoding: [0x41,0xfc,0x11,0x9e]
; CHECK: fcvtmu x1, d2 ; encoding: [0x41,0x00,0x71,0x9e]
-; CHECK: fcvtmu x1, d2, #1 ; encoding: [0x41,0xfc,0x51,0x9e]
fcvtns w1, s2
- fcvtns w1, s2, #1
fcvtns w1, d2
- fcvtns w1, d2, #1
fcvtns x1, s2
- fcvtns x1, s2, #1
fcvtns x1, d2
- fcvtns x1, d2, #1
; CHECK: fcvtns w1, s2 ; encoding: [0x41,0x00,0x20,0x1e]
-; CHECK: fcvtns w1, s2, #1 ; encoding: [0x41,0xfc,0x00,0x1e]
; CHECK: fcvtns w1, d2 ; encoding: [0x41,0x00,0x60,0x1e]
-; CHECK: fcvtns w1, d2, #1 ; encoding: [0x41,0xfc,0x40,0x1e]
; CHECK: fcvtns x1, s2 ; encoding: [0x41,0x00,0x20,0x9e]
-; CHECK: fcvtns x1, s2, #1 ; encoding: [0x41,0xfc,0x00,0x9e]
; CHECK: fcvtns x1, d2 ; encoding: [0x41,0x00,0x60,0x9e]
-; CHECK: fcvtns x1, d2, #1 ; encoding: [0x41,0xfc,0x40,0x9e]
fcvtnu w1, s2
- fcvtnu w1, s2, #1
fcvtnu w1, d2
- fcvtnu w1, d2, #1
fcvtnu x1, s2
- fcvtnu x1, s2, #1
fcvtnu x1, d2
- fcvtnu x1, d2, #1
; CHECK: fcvtnu w1, s2 ; encoding: [0x41,0x00,0x21,0x1e]
-; CHECK: fcvtnu w1, s2, #1 ; encoding: [0x41,0xfc,0x01,0x1e]
; CHECK: fcvtnu w1, d2 ; encoding: [0x41,0x00,0x61,0x1e]
-; CHECK: fcvtnu w1, d2, #1 ; encoding: [0x41,0xfc,0x41,0x1e]
; CHECK: fcvtnu x1, s2 ; encoding: [0x41,0x00,0x21,0x9e]
-; CHECK: fcvtnu x1, s2, #1 ; encoding: [0x41,0xfc,0x01,0x9e]
; CHECK: fcvtnu x1, d2 ; encoding: [0x41,0x00,0x61,0x9e]
-; CHECK: fcvtnu x1, d2, #1 ; encoding: [0x41,0xfc,0x41,0x9e]
fcvtps w1, s2
- fcvtps w1, s2, #1
fcvtps w1, d2
- fcvtps w1, d2, #1
fcvtps x1, s2
- fcvtps x1, s2, #1
fcvtps x1, d2
- fcvtps x1, d2, #1
; CHECK: fcvtps w1, s2 ; encoding: [0x41,0x00,0x28,0x1e]
-; CHECK: fcvtps w1, s2, #1 ; encoding: [0x41,0xfc,0x08,0x1e]
; CHECK: fcvtps w1, d2 ; encoding: [0x41,0x00,0x68,0x1e]
-; CHECK: fcvtps w1, d2, #1 ; encoding: [0x41,0xfc,0x48,0x1e]
; CHECK: fcvtps x1, s2 ; encoding: [0x41,0x00,0x28,0x9e]
-; CHECK: fcvtps x1, s2, #1 ; encoding: [0x41,0xfc,0x08,0x9e]
; CHECK: fcvtps x1, d2 ; encoding: [0x41,0x00,0x68,0x9e]
-; CHECK: fcvtps x1, d2, #1 ; encoding: [0x41,0xfc,0x48,0x9e]
fcvtpu w1, s2
- fcvtpu w1, s2, #1
fcvtpu w1, d2
- fcvtpu w1, d2, #1
fcvtpu x1, s2
- fcvtpu x1, s2, #1
fcvtpu x1, d2
- fcvtpu x1, d2, #1
; CHECK: fcvtpu w1, s2 ; encoding: [0x41,0x00,0x29,0x1e]
-; CHECK: fcvtpu w1, s2, #1 ; encoding: [0x41,0xfc,0x09,0x1e]
; CHECK: fcvtpu w1, d2 ; encoding: [0x41,0x00,0x69,0x1e]
-; CHECK: fcvtpu w1, d2, #1 ; encoding: [0x41,0xfc,0x49,0x1e]
; CHECK: fcvtpu x1, s2 ; encoding: [0x41,0x00,0x29,0x9e]
-; CHECK: fcvtpu x1, s2, #1 ; encoding: [0x41,0xfc,0x09,0x9e]
; CHECK: fcvtpu x1, d2 ; encoding: [0x41,0x00,0x69,0x9e]
-; CHECK: fcvtpu x1, d2, #1 ; encoding: [0x41,0xfc,0x49,0x9e]
fcvtzs w1, s2
fcvtzs w1, s2, #1
diff --git a/test/MC/ARM64/memory.s b/test/MC/ARM64/memory.s
index 0e8f1d5..47188c6 100644
--- a/test/MC/ARM64/memory.s
+++ b/test/MC/ARM64/memory.s
@@ -208,32 +208,32 @@ foo:
; Pre-indexed loads and stores
;-----------------------------------------------------------------------------
- ldr fp, [x7, #8]!
- ldr lr, [x7, #8]!
+ ldr x29, [x7, #8]!
+ ldr x30, [x7, #8]!
ldr b5, [x0, #1]!
ldr h6, [x0, #2]!
ldr s7, [x0, #4]!
ldr d8, [x0, #8]!
ldr q9, [x0, #16]!
- str lr, [x7, #-8]!
- str fp, [x7, #-8]!
+ str x30, [x7, #-8]!
+ str x29, [x7, #-8]!
str b5, [x0, #-1]!
str h6, [x0, #-2]!
str s7, [x0, #-4]!
str d8, [x0, #-8]!
str q9, [x0, #-16]!
-; CHECK: ldr fp, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8]
-; CHECK: ldr lr, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8]
+; CHECK: ldr x29, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8]
+; CHECK: ldr x30, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8]
; CHECK: ldr b5, [x0, #1]! ; encoding: [0x05,0x1c,0x40,0x3c]
; CHECK: ldr h6, [x0, #2]! ; encoding: [0x06,0x2c,0x40,0x7c]
; CHECK: ldr s7, [x0, #4]! ; encoding: [0x07,0x4c,0x40,0xbc]
; CHECK: ldr d8, [x0, #8]! ; encoding: [0x08,0x8c,0x40,0xfc]
; CHECK: ldr q9, [x0, #16]! ; encoding: [0x09,0x0c,0xc1,0x3c]
-; CHECK: str lr, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8]
-; CHECK: str fp, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8]
+; CHECK: str x30, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8]
+; CHECK: str x29, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8]
; CHECK: str b5, [x0, #-1]! ; encoding: [0x05,0xfc,0x1f,0x3c]
; CHECK: str h6, [x0, #-2]! ; encoding: [0x06,0xec,0x1f,0x7c]
; CHECK: str s7, [x0, #-4]! ; encoding: [0x07,0xcc,0x1f,0xbc]
@@ -243,32 +243,32 @@ foo:
;-----------------------------------------------------------------------------
; post-indexed loads and stores
;-----------------------------------------------------------------------------
- str lr, [x7], #-8
- str fp, [x7], #-8
+ str x30, [x7], #-8
+ str x29, [x7], #-8
str b5, [x0], #-1
str h6, [x0], #-2
str s7, [x0], #-4
str d8, [x0], #-8
str q9, [x0], #-16
- ldr fp, [x7], #8
- ldr lr, [x7], #8
+ ldr x29, [x7], #8
+ ldr x30, [x7], #8
ldr b5, [x0], #1
ldr h6, [x0], #2
ldr s7, [x0], #4
ldr d8, [x0], #8
ldr q9, [x0], #16
-; CHECK: str lr, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8]
-; CHECK: str fp, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8]
+; CHECK: str x30, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8]
+; CHECK: str x29, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8]
; CHECK: str b5, [x0], #-1 ; encoding: [0x05,0xf4,0x1f,0x3c]
; CHECK: str h6, [x0], #-2 ; encoding: [0x06,0xe4,0x1f,0x7c]
; CHECK: str s7, [x0], #-4 ; encoding: [0x07,0xc4,0x1f,0xbc]
; CHECK: str d8, [x0], #-8 ; encoding: [0x08,0x84,0x1f,0xfc]
; CHECK: str q9, [x0], #-16 ; encoding: [0x09,0x04,0x9f,0x3c]
-; CHECK: ldr fp, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8]
-; CHECK: ldr lr, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8]
+; CHECK: ldr x29, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8]
+; CHECK: ldr x30, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8]
; CHECK: ldr b5, [x0], #1 ; encoding: [0x05,0x14,0x40,0x3c]
; CHECK: ldr h6, [x0], #2 ; encoding: [0x06,0x24,0x40,0x7c]
; CHECK: ldr s7, [x0], #4 ; encoding: [0x07,0x44,0x40,0xbc]
@@ -545,8 +545,8 @@ foo:
; unambiguous, i.e. negative or unaligned."
;-----------------------------------------------------------------------------
- ldr x11, [fp, #-8]
- ldr x11, [fp, #7]
+ ldr x11, [x29, #-8]
+ ldr x11, [x29, #7]
ldr w0, [x0, #2]
ldr w0, [x0, #-256]
ldr b2, [x1, #-2]
@@ -559,8 +559,8 @@ foo:
ldr q5, [x8, #8]
ldr q5, [x9, #-16]
-; CHECK: ldur x11, [fp, #-8] ; encoding: [0xab,0x83,0x5f,0xf8]
-; CHECK: ldur x11, [fp, #7] ; encoding: [0xab,0x73,0x40,0xf8]
+; CHECK: ldur x11, [x29, #-8] ; encoding: [0xab,0x83,0x5f,0xf8]
+; CHECK: ldur x11, [x29, #7] ; encoding: [0xab,0x73,0x40,0xf8]
; CHECK: ldur w0, [x0, #2] ; encoding: [0x00,0x20,0x40,0xb8]
; CHECK: ldur w0, [x0, #-256] ; encoding: [0x00,0x00,0x50,0xb8]
; CHECK: ldur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x5f,0x3c]
@@ -573,8 +573,8 @@ foo:
; CHECK: ldur q5, [x8, #8] ; encoding: [0x05,0x81,0xc0,0x3c]
; CHECK: ldur q5, [x9, #-16] ; encoding: [0x25,0x01,0xdf,0x3c]
- str x11, [fp, #-8]
- str x11, [fp, #7]
+ str x11, [x29, #-8]
+ str x11, [x29, #7]
str w0, [x0, #2]
str w0, [x0, #-256]
str b2, [x1, #-2]
@@ -587,8 +587,8 @@ foo:
str q5, [x8, #8]
str q5, [x9, #-16]
-; CHECK: stur x11, [fp, #-8] ; encoding: [0xab,0x83,0x1f,0xf8]
-; CHECK: stur x11, [fp, #7] ; encoding: [0xab,0x73,0x00,0xf8]
+; CHECK: stur x11, [x29, #-8] ; encoding: [0xab,0x83,0x1f,0xf8]
+; CHECK: stur x11, [x29, #7] ; encoding: [0xab,0x73,0x00,0xf8]
; CHECK: stur w0, [x0, #2] ; encoding: [0x00,0x20,0x00,0xb8]
; CHECK: stur w0, [x0, #-256] ; encoding: [0x00,0x00,0x10,0xb8]
; CHECK: stur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x1f,0x3c]
diff --git a/test/MC/ARM64/nv-cond.s b/test/MC/ARM64/nv-cond.s
new file mode 100644
index 0000000..ded5ec6
--- /dev/null
+++ b/test/MC/ARM64/nv-cond.s
@@ -0,0 +1,11 @@
+// RUN: llvm-mc < %s -triple arm64 -show-encoding | FileCheck %s
+
+fcsel d28,d31,d31,nv
+csel x0,x0,x0,nv
+ccmp x0,x0,#0,nv
+b.nv #0
+
+// CHECK: fcsel d28, d31, d31, nv // encoding: [0xfc,0xff,0x7f,0x1e]
+// CHECK: csel x0, x0, x0, nv // encoding: [0x00,0xf0,0x80,0x9a]
+// CHECK: ccmp x0, x0, #0, nv // encoding: [0x00,0xf0,0x40,0xfa]
+// CHECK: b.nv #0 // encoding: [0x0f,0x00,0x00,0x54]
diff --git a/test/MC/ARM64/simd-ldst.s b/test/MC/ARM64/simd-ldst.s
index a754c72..75d0383 100644
--- a/test/MC/ARM64/simd-ldst.s
+++ b/test/MC/ARM64/simd-ldst.s
@@ -263,10 +263,10 @@ ld3st3_multiple:
; CHECK: ld3.8b { v9, v10, v11 }, [x9] ; encoding: [0x29,0x41,0x40,0x0c]
; CHECK: ld3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x40,0x4c]
-; CHECK: ld3.4h { v24, v25, v26 }, [fp] ; encoding: [0xb8,0x47,0x40,0x0c]
+; CHECK: ld3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x40,0x0c]
; CHECK: ld3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x40,0x4c]
; CHECK: ld3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x0c]
-; CHECK: ld3.4s { v4, v5, v6 }, [fp] ; encoding: [0xa4,0x4b,0x40,0x4c]
+; CHECK: ld3.4s { v4, v5, v6 }, [x29] ; encoding: [0xa4,0x4b,0x40,0x4c]
; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c]
; CHECK: st3.8b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x00,0x0c]
@@ -279,10 +279,10 @@ ld3st3_multiple:
; CHECK: st3.8b { v10, v11, v12 }, [x9] ; encoding: [0x2a,0x41,0x00,0x0c]
; CHECK: st3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x00,0x4c]
-; CHECK: st3.4h { v24, v25, v26 }, [fp] ; encoding: [0xb8,0x47,0x00,0x0c]
+; CHECK: st3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x00,0x0c]
; CHECK: st3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x00,0x4c]
; CHECK: st3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x0c]
-; CHECK: st3.4s { v7, v8, v9 }, [fp] ; encoding: [0xa7,0x4b,0x00,0x4c]
+; CHECK: st3.4s { v7, v8, v9 }, [x29] ; encoding: [0xa7,0x4b,0x00,0x4c]
; CHECK: st3.2d { v4, v5, v6 }, [x9] ; encoding: [0x24,0x4d,0x00,0x4c]
ld4st4_multiple:
diff --git a/test/MC/ARM64/spsel-sysreg.s b/test/MC/ARM64/spsel-sysreg.s
new file mode 100644
index 0000000..e6ff4bf
--- /dev/null
+++ b/test/MC/ARM64/spsel-sysreg.s
@@ -0,0 +1,24 @@
+// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+msr SPSel, #0
+msr SPSel, x0
+msr DAIFSet, #0
+msr ESR_EL1, x0
+mrs x0, SPSel
+mrs x0, ESR_EL1
+
+// CHECK: msr SPSEL, #0 // encoding: [0xbf,0x40,0x00,0xd5]
+// CHECK: msr SPSEL, x0 // encoding: [0x00,0x42,0x18,0xd5]
+// CHECK: msr DAIFSET, #0 // encoding: [0xdf,0x40,0x03,0xd5]
+// CHECK: msr ESR_EL1, x0 // encoding: [0x00,0x52,0x18,0xd5]
+// CHECK: mrs x0, SPSEL // encoding: [0x00,0x42,0x38,0xd5]
+// CHECK: mrs x0, ESR_EL1 // encoding: [0x00,0x52,0x38,0xd5]
+
+
+msr DAIFSet, x0
+msr ESR_EL1, #0
+mrs x0, DAIFSet
+// CHECK-ERRORS: error: invalid operand for instruction
+// CHECK-ERRORS: error: invalid operand for instruction
+// CHECK-ERRORS: error: invalid operand for instruction
diff --git a/test/MC/ARM64/system-encoding.s b/test/MC/ARM64/system-encoding.s
index 9f0d3c4..9b3238b 100644
--- a/test/MC/ARM64/system-encoding.s
+++ b/test/MC/ARM64/system-encoding.s
@@ -60,29 +60,24 @@ foo:
msr ACTLR_EL1, x3
msr ACTLR_EL2, x3
msr ACTLR_EL3, x3
- msr ADFSR_EL1, x3
- msr ADFSR_EL2, x3
- msr ADFSR_EL3, x3
- msr AIDR_EL1, x3
- msr AIFSR_EL1, x3
- msr AIFSR_EL2, x3
- msr AIFSR_EL3, x3
+ msr AFSR0_EL1, x3
+ msr AFSR0_EL2, x3
+ msr AFSR0_EL3, x3
+ msr AFSR1_EL1, x3
+ msr AFSR1_EL2, x3
+ msr AFSR1_EL3, x3
msr AMAIR_EL1, x3
msr AMAIR_EL2, x3
msr AMAIR_EL3, x3
- msr CCSIDR_EL1, x3
- msr CLIDR_EL1, x3
msr CNTFRQ_EL0, x3
msr CNTHCTL_EL2, x3
msr CNTHP_CTL_EL2, x3
msr CNTHP_CVAL_EL2, x3
msr CNTHP_TVAL_EL2, x3
msr CNTKCTL_EL1, x3
- msr CNTPCT_EL0, x3
msr CNTP_CTL_EL0, x3
msr CNTP_CVAL_EL0, x3
msr CNTP_TVAL_EL0, x3
- msr CNTVCT_EL0, x3
msr CNTVOFF_EL2, x3
msr CNTV_CTL_EL0, x3
msr CNTV_CVAL_EL0, x3
@@ -92,11 +87,8 @@ foo:
msr CPTR_EL2, x3
msr CPTR_EL3, x3
msr CSSELR_EL1, x3
- msr CTR_EL0, x3
- msr CURRENT_EL, x3
+ msr CURRENTEL, x3
msr DACR32_EL2, x3
- msr DCZID_EL0, x3
- msr ECOIDR_EL1, x3
msr ESR_EL1, x3
msr ESR_EL2, x3
msr ESR_EL3, x3
@@ -108,29 +100,13 @@ foo:
msr HCR_EL2, x3
msr HPFAR_EL2, x3
msr HSTR_EL2, x3
- msr ID_AA64DFR0_EL1, x3
- msr ID_AA64DFR1_EL1, x3
- msr ID_AA64ISAR0_EL1, x3
- msr ID_AA64ISAR1_EL1, x3
- msr ID_AA64MMFR0_EL1, x3
- msr ID_AA64MMFR1_EL1, x3
- msr ID_AA64PFR0_EL1, x3
- msr ID_AA64PFR1_EL1, x3
msr IFSR32_EL2, x3
- msr ISR_EL1, x3
msr MAIR_EL1, x3
msr MAIR_EL2, x3
msr MAIR_EL3, x3
msr MDCR_EL2, x3
msr MDCR_EL3, x3
- msr MIDR_EL1, x3
- msr MPIDR_EL1, x3
- msr MVFR0_EL1, x3
- msr MVFR1_EL1, x3
msr PAR_EL1, x3
- msr RVBAR_EL1, x3
- msr RVBAR_EL2, x3
- msr RVBAR_EL3, x3
msr SCR_EL3, x3
msr SCTLR_EL1, x3
msr SCTLR_EL2, x3
@@ -158,33 +134,28 @@ foo:
msr VTCR_EL2, x3
msr VTTBR_EL2, x3
msr SPSel, x3
- msr S2_2_C4_C6_4, x1
+ msr S3_2_C11_C6_4, x1
; CHECK: msr ACTLR_EL1, x3 ; encoding: [0x23,0x10,0x18,0xd5]
; CHECK: msr ACTLR_EL2, x3 ; encoding: [0x23,0x10,0x1c,0xd5]
; CHECK: msr ACTLR_EL3, x3 ; encoding: [0x23,0x10,0x1e,0xd5]
; CHECK: msr AFSR0_EL1, x3 ; encoding: [0x03,0x51,0x18,0xd5]
-; CHECK: msr ADFSR_EL2, x3 ; encoding: [0x03,0x51,0x1c,0xd5]
-; CHECK: msr ADFSR_EL3, x3 ; encoding: [0x03,0x51,0x1e,0xd5]
-; CHECK: msr AIDR_EL1, x3 ; encoding: [0xe3,0x00,0x19,0xd5]
+; CHECK: msr AFSR0_EL2, x3 ; encoding: [0x03,0x51,0x1c,0xd5]
+; CHECK: msr AFSR0_EL3, x3 ; encoding: [0x03,0x51,0x1e,0xd5]
; CHECK: msr AFSR1_EL1, x3 ; encoding: [0x23,0x51,0x18,0xd5]
-; CHECK: msr AIFSR_EL2, x3 ; encoding: [0x23,0x51,0x1c,0xd5]
-; CHECK: msr AIFSR_EL3, x3 ; encoding: [0x23,0x51,0x1e,0xd5]
+; CHECK: msr AFSR1_EL2, x3 ; encoding: [0x23,0x51,0x1c,0xd5]
+; CHECK: msr AFSR1_EL3, x3 ; encoding: [0x23,0x51,0x1e,0xd5]
; CHECK: msr AMAIR_EL1, x3 ; encoding: [0x03,0xa3,0x18,0xd5]
; CHECK: msr AMAIR_EL2, x3 ; encoding: [0x03,0xa3,0x1c,0xd5]
; CHECK: msr AMAIR_EL3, x3 ; encoding: [0x03,0xa3,0x1e,0xd5]
-; CHECK: msr CCSIDR_EL1, x3 ; encoding: [0x03,0x00,0x19,0xd5]
-; CHECK: msr CLIDR_EL1, x3 ; encoding: [0x23,0x00,0x19,0xd5]
; CHECK: msr CNTFRQ_EL0, x3 ; encoding: [0x03,0xe0,0x1b,0xd5]
; CHECK: msr CNTHCTL_EL2, x3 ; encoding: [0x03,0xe1,0x1c,0xd5]
; CHECK: msr CNTHP_CTL_EL2, x3 ; encoding: [0x23,0xe2,0x1c,0xd5]
; CHECK: msr CNTHP_CVAL_EL2, x3 ; encoding: [0x43,0xe2,0x1c,0xd5]
; CHECK: msr CNTHP_TVAL_EL2, x3 ; encoding: [0x03,0xe2,0x1c,0xd5]
; CHECK: msr CNTKCTL_EL1, x3 ; encoding: [0x03,0xe1,0x18,0xd5]
-; CHECK: msr CNTPCT_EL0, x3 ; encoding: [0x23,0xe0,0x1b,0xd5]
; CHECK: msr CNTP_CTL_EL0, x3 ; encoding: [0x23,0xe2,0x1b,0xd5]
; CHECK: msr CNTP_CVAL_EL0, x3 ; encoding: [0x43,0xe2,0x1b,0xd5]
; CHECK: msr CNTP_TVAL_EL0, x3 ; encoding: [0x03,0xe2,0x1b,0xd5]
-; CHECK: msr CNTVCT_EL0, x3 ; encoding: [0x43,0xe0,0x1b,0xd5]
; CHECK: msr CNTVOFF_EL2, x3 ; encoding: [0x63,0xe0,0x1c,0xd5]
; CHECK: msr CNTV_CTL_EL0, x3 ; encoding: [0x23,0xe3,0x1b,0xd5]
; CHECK: msr CNTV_CVAL_EL0, x3 ; encoding: [0x43,0xe3,0x1b,0xd5]
@@ -194,11 +165,8 @@ foo:
; CHECK: msr CPTR_EL2, x3 ; encoding: [0x43,0x11,0x1c,0xd5]
; CHECK: msr CPTR_EL3, x3 ; encoding: [0x43,0x11,0x1e,0xd5]
; CHECK: msr CSSELR_EL1, x3 ; encoding: [0x03,0x00,0x1a,0xd5]
-; CHECK: msr CTR_EL0, x3 ; encoding: [0x23,0x00,0x1b,0xd5]
-; CHECK: msr CurrentEL, x3 ; encoding: [0x43,0x42,0x18,0xd5]
+; CHECK: msr CURRENTEL, x3 ; encoding: [0x43,0x42,0x18,0xd5]
; CHECK: msr DACR32_EL2, x3 ; encoding: [0x03,0x30,0x1c,0xd5]
-; CHECK: msr DCZID_EL0, x3 ; encoding: [0xe3,0x00,0x1b,0xd5]
-; CHECK: msr REVIDR_EL1, x3 ; encoding: [0xc3,0x00,0x18,0xd5]
; CHECK: msr ESR_EL1, x3 ; encoding: [0x03,0x52,0x18,0xd5]
; CHECK: msr ESR_EL2, x3 ; encoding: [0x03,0x52,0x1c,0xd5]
; CHECK: msr ESR_EL3, x3 ; encoding: [0x03,0x52,0x1e,0xd5]
@@ -210,29 +178,13 @@ foo:
; CHECK: msr HCR_EL2, x3 ; encoding: [0x03,0x11,0x1c,0xd5]
; CHECK: msr HPFAR_EL2, x3 ; encoding: [0x83,0x60,0x1c,0xd5]
; CHECK: msr HSTR_EL2, x3 ; encoding: [0x63,0x11,0x1c,0xd5]
-; CHECK: msr ID_AA64DFR0_EL1, x3 ; encoding: [0x03,0x05,0x18,0xd5]
-; CHECK: msr ID_AA64DFR1_EL1, x3 ; encoding: [0x23,0x05,0x18,0xd5]
-; CHECK: msr ID_AA64ISAR0_EL1, x3 ; encoding: [0x03,0x06,0x18,0xd5]
-; CHECK: msr ID_AA64ISAR1_EL1, x3 ; encoding: [0x23,0x06,0x18,0xd5]
-; CHECK: msr ID_AA64MMFR0_EL1, x3 ; encoding: [0x03,0x07,0x18,0xd5]
-; CHECK: msr ID_AA64MMFR1_EL1, x3 ; encoding: [0x23,0x07,0x18,0xd5]
-; CHECK: msr ID_AA64PFR0_EL1, x3 ; encoding: [0x03,0x04,0x18,0xd5]
-; CHECK: msr ID_AA64PFR1_EL1, x3 ; encoding: [0x23,0x04,0x18,0xd5]
; CHECK: msr IFSR32_EL2, x3 ; encoding: [0x23,0x50,0x1c,0xd5]
-; CHECK: msr ISR_EL1, x3 ; encoding: [0x03,0xc1,0x18,0xd5]
; CHECK: msr MAIR_EL1, x3 ; encoding: [0x03,0xa2,0x18,0xd5]
; CHECK: msr MAIR_EL2, x3 ; encoding: [0x03,0xa2,0x1c,0xd5]
; CHECK: msr MAIR_EL3, x3 ; encoding: [0x03,0xa2,0x1e,0xd5]
; CHECK: msr MDCR_EL2, x3 ; encoding: [0x23,0x11,0x1c,0xd5]
; CHECK: msr MDCR_EL3, x3 ; encoding: [0x23,0x13,0x1e,0xd5]
-; CHECK: msr MIDR_EL1, x3 ; encoding: [0x03,0x00,0x18,0xd5]
-; CHECK: msr MPIDR_EL1, x3 ; encoding: [0xa3,0x00,0x18,0xd5]
-; CHECK: msr MVFR0_EL1, x3 ; encoding: [0x03,0x03,0x18,0xd5]
-; CHECK: msr MVFR1_EL1, x3 ; encoding: [0x23,0x03,0x18,0xd5]
; CHECK: msr PAR_EL1, x3 ; encoding: [0x03,0x74,0x18,0xd5]
-; CHECK: msr RVBAR_EL1, x3 ; encoding: [0x23,0xc0,0x18,0xd5]
-; CHECK: msr RVBAR_EL2, x3 ; encoding: [0x23,0xc0,0x1c,0xd5]
-; CHECK: msr RVBAR_EL3, x3 ; encoding: [0x23,0xc0,0x1e,0xd5]
; CHECK: msr SCR_EL3, x3 ; encoding: [0x03,0x11,0x1e,0xd5]
; CHECK: msr SCTLR_EL1, x3 ; encoding: [0x03,0x10,0x18,0xd5]
; CHECK: msr SCTLR_EL2, x3 ; encoding: [0x03,0x10,0x1c,0xd5]
@@ -259,19 +211,19 @@ foo:
; CHECK: msr VPIDR_EL2, x3 ; encoding: [0x03,0x00,0x1c,0xd5]
; CHECK: msr VTCR_EL2, x3 ; encoding: [0x43,0x21,0x1c,0xd5]
; CHECK: msr VTTBR_EL2, x3 ; encoding: [0x03,0x21,0x1c,0xd5]
-; CHECK: msr SPSel, x3 ; encoding: [0x03,0x42,0x18,0xd5]
-; CHECK: msr S2_2_C4_C6_4, x1 ; encoding: [0x81,0x46,0x12,0xd5]
+; CHECK: msr SPSEL, x3 ; encoding: [0x03,0x42,0x18,0xd5]
+; CHECK: msr S3_2_C11_C6_4, x1 ; encoding: [0x81,0xb6,0x1a,0xd5]
mrs x3, ACTLR_EL1
mrs x3, ACTLR_EL2
mrs x3, ACTLR_EL3
- mrs x3, ADFSR_EL1
- mrs x3, ADFSR_EL2
- mrs x3, ADFSR_EL3
+ mrs x3, AFSR0_EL1
+ mrs x3, AFSR0_EL2
+ mrs x3, AFSR0_EL3
mrs x3, AIDR_EL1
- mrs x3, AIFSR_EL1
- mrs x3, AIFSR_EL2
- mrs x3, AIFSR_EL3
+ mrs x3, AFSR1_EL1
+ mrs x3, AFSR1_EL2
+ mrs x3, AFSR1_EL3
mrs x3, AMAIR_EL1
mrs x3, AMAIR_EL2
mrs x3, AMAIR_EL3
@@ -298,10 +250,10 @@ foo:
mrs x3, CPTR_EL3
mrs x3, CSSELR_EL1
mrs x3, CTR_EL0
- mrs x3, CURRENT_EL
+ mrs x3, CURRENTEL
mrs x3, DACR32_EL2
mrs x3, DCZID_EL0
- mrs x3, ECOIDR_EL1
+ mrs x3, REVIDR_EL1
mrs x3, ESR_EL1
mrs x3, ESR_EL2
mrs x3, ESR_EL3
@@ -367,12 +319,11 @@ foo:
mrs x3, MDCCINT_EL1
mrs x3, DBGDTR_EL0
mrs x3, DBGDTRRX_EL0
- mrs x3, DBGDTRTX_EL0
mrs x3, DBGVCR32_EL2
mrs x3, OSDTRRX_EL1
mrs x3, MDSCR_EL1
mrs x3, OSDTRTX_EL1
- mrs x3, OSECCR_EL11
+ mrs x3, OSECCR_EL1
mrs x3, DBGBVR0_EL1
mrs x3, DBGBVR1_EL1
mrs x3, DBGBVR2_EL1
@@ -438,30 +389,26 @@ foo:
mrs x3, DBGWCR14_EL1
mrs x3, DBGWCR15_EL1
mrs x3, MDRAR_EL1
- mrs x3, OSLAR_EL1
mrs x3, OSLSR_EL1
mrs x3, OSDLR_EL1
mrs x3, DBGPRCR_EL1
mrs x3, DBGCLAIMSET_EL1
mrs x3, DBGCLAIMCLR_EL1
mrs x3, DBGAUTHSTATUS_EL1
- mrs x3, DBGDEVID2
- mrs x3, DBGDEVID1
- mrs x3, DBGDEVID0
- mrs x1, S2_2_C4_C6_4
- mrs x3, s2_3_c2_c1_4
- mrs x3, S2_3_c2_c1_4
+ mrs x1, S3_2_C15_C6_4
+ mrs x3, s3_3_c11_c1_4
+ mrs x3, S3_3_c11_c1_4
; CHECK: mrs x3, ACTLR_EL1 ; encoding: [0x23,0x10,0x38,0xd5]
; CHECK: mrs x3, ACTLR_EL2 ; encoding: [0x23,0x10,0x3c,0xd5]
; CHECK: mrs x3, ACTLR_EL3 ; encoding: [0x23,0x10,0x3e,0xd5]
; CHECK: mrs x3, AFSR0_EL1 ; encoding: [0x03,0x51,0x38,0xd5]
-; CHECK: mrs x3, ADFSR_EL2 ; encoding: [0x03,0x51,0x3c,0xd5]
-; CHECK: mrs x3, ADFSR_EL3 ; encoding: [0x03,0x51,0x3e,0xd5]
+; CHECK: mrs x3, AFSR0_EL2 ; encoding: [0x03,0x51,0x3c,0xd5]
+; CHECK: mrs x3, AFSR0_EL3 ; encoding: [0x03,0x51,0x3e,0xd5]
; CHECK: mrs x3, AIDR_EL1 ; encoding: [0xe3,0x00,0x39,0xd5]
; CHECK: mrs x3, AFSR1_EL1 ; encoding: [0x23,0x51,0x38,0xd5]
-; CHECK: mrs x3, AIFSR_EL2 ; encoding: [0x23,0x51,0x3c,0xd5]
-; CHECK: mrs x3, AIFSR_EL3 ; encoding: [0x23,0x51,0x3e,0xd5]
+; CHECK: mrs x3, AFSR1_EL2 ; encoding: [0x23,0x51,0x3c,0xd5]
+; CHECK: mrs x3, AFSR1_EL3 ; encoding: [0x23,0x51,0x3e,0xd5]
; CHECK: mrs x3, AMAIR_EL1 ; encoding: [0x03,0xa3,0x38,0xd5]
; CHECK: mrs x3, AMAIR_EL2 ; encoding: [0x03,0xa3,0x3c,0xd5]
; CHECK: mrs x3, AMAIR_EL3 ; encoding: [0x03,0xa3,0x3e,0xd5]
@@ -488,7 +435,7 @@ foo:
; CHECK: mrs x3, CPTR_EL3 ; encoding: [0x43,0x11,0x3e,0xd5]
; CHECK: mrs x3, CSSELR_EL1 ; encoding: [0x03,0x00,0x3a,0xd5]
; CHECK: mrs x3, CTR_EL0 ; encoding: [0x23,0x00,0x3b,0xd5]
-; CHECK: mrs x3, CurrentEL ; encoding: [0x43,0x42,0x38,0xd5]
+; CHECK: mrs x3, CURRENTEL ; encoding: [0x43,0x42,0x38,0xd5]
; CHECK: mrs x3, DACR32_EL2 ; encoding: [0x03,0x30,0x3c,0xd5]
; CHECK: mrs x3, DCZID_EL0 ; encoding: [0xe3,0x00,0x3b,0xd5]
; CHECK: mrs x3, REVIDR_EL1 ; encoding: [0xc3,0x00,0x38,0xd5]
@@ -556,12 +503,11 @@ foo:
; CHECK: mrs x3, MDCCINT_EL1 ; encoding: [0x03,0x02,0x30,0xd5]
; CHECK: mrs x3, DBGDTR_EL0 ; encoding: [0x03,0x04,0x33,0xd5]
; CHECK: mrs x3, DBGDTRRX_EL0 ; encoding: [0x03,0x05,0x33,0xd5]
-; CHECK: mrs x3, DBGDTRRX_EL0 ; encoding: [0x03,0x05,0x33,0xd5]
; CHECK: mrs x3, DBGVCR32_EL2 ; encoding: [0x03,0x07,0x34,0xd5]
; CHECK: mrs x3, OSDTRRX_EL1 ; encoding: [0x43,0x00,0x30,0xd5]
; CHECK: mrs x3, MDSCR_EL1 ; encoding: [0x43,0x02,0x30,0xd5]
; CHECK: mrs x3, OSDTRTX_EL1 ; encoding: [0x43,0x03,0x30,0xd5]
-; CHECK: mrs x3, OSECCR_EL11 ; encoding: [0x43,0x06,0x30,0xd5]
+; CHECK: mrs x3, OSECCR_EL1 ; encoding: [0x43,0x06,0x30,0xd5]
; CHECK: mrs x3, DBGBVR0_EL1 ; encoding: [0x83,0x00,0x30,0xd5]
; CHECK: mrs x3, DBGBVR1_EL1 ; encoding: [0x83,0x01,0x30,0xd5]
; CHECK: mrs x3, DBGBVR2_EL1 ; encoding: [0x83,0x02,0x30,0xd5]
@@ -627,30 +573,30 @@ foo:
; CHECK: mrs x3, DBGWCR14_EL1 ; encoding: [0xe3,0x0e,0x30,0xd5]
; CHECK: mrs x3, DBGWCR15_EL1 ; encoding: [0xe3,0x0f,0x30,0xd5]
; CHECK: mrs x3, MDRAR_EL1 ; encoding: [0x03,0x10,0x30,0xd5]
-; CHECK: mrs x3, OSLAR_EL1 ; encoding: [0x83,0x10,0x30,0xd5]
; CHECK: mrs x3, OSLSR_EL1 ; encoding: [0x83,0x11,0x30,0xd5]
; CHECK: mrs x3, OSDLR_EL1 ; encoding: [0x83,0x13,0x30,0xd5]
; CHECK: mrs x3, DBGPRCR_EL1 ; encoding: [0x83,0x14,0x30,0xd5]
; CHECK: mrs x3, DBGCLAIMSET_EL1 ; encoding: [0xc3,0x78,0x30,0xd5]
; CHECK: mrs x3, DBGCLAIMCLR_EL1 ; encoding: [0xc3,0x79,0x30,0xd5]
; CHECK: mrs x3, DBGAUTHSTATUS_EL1 ; encoding: [0xc3,0x7e,0x30,0xd5]
-; CHECK: mrs x3, DBGDEVID2 ; encoding: [0xe3,0x70,0x30,0xd5]
-; CHECK: mrs x3, DBGDEVID1 ; encoding: [0xe3,0x71,0x30,0xd5]
-; CHECK: mrs x3, DBGDEVID0 ; encoding: [0xe3,0x72,0x30,0xd5]
-; CHECK: mrs x1, S2_2_C4_C6_4 ; encoding: [0x81,0x46,0x32,0xd5]
-; CHECK: mrs x3, S2_3_C2_C1_4 ; encoding: [0x83,0x21,0x33,0xd5]
-; CHECK: mrs x3, S2_3_C2_C1_4 ; encoding: [0x83,0x21,0x33,0xd5]
+; CHECK: mrs x1, S3_2_C15_C6_4 ; encoding: [0x81,0xf6,0x3a,0xd5]
+; CHECK: mrs x3, S3_3_C11_C1_4 ; encoding: [0x83,0xb1,0x3b,0xd5]
+; CHECK: mrs x3, S3_3_C11_C1_4 ; encoding: [0x83,0xb1,0x3b,0xd5]
msr RMR_EL3, x0
msr RMR_EL2, x0
msr RMR_EL1, x0
msr CPM_IOACC_CTL_EL3, x0
-
+ msr OSLAR_EL1, x3
+ msr DBGDTRTX_EL0, x3
+
; CHECK: msr RMR_EL3, x0 ; encoding: [0x40,0xc0,0x1e,0xd5]
-; CHECK: msr RMR_EL2, x0 ; encoding: [0x40,0xc0,0x1a,0xd5]
-; CHECK: msr RMR_EL1, x0 ; encoding: [0x40,0xc0,0x19,0xd5]
+; CHECK: msr RMR_EL2, x0 ; encoding: [0x40,0xc0,0x1c,0xd5]
+; CHECK: msr RMR_EL1, x0 ; encoding: [0x40,0xc0,0x18,0xd5]
; CHECK: msr CPM_IOACC_CTL_EL3, x0 ; encoding: [0x00,0xf2,0x1f,0xd5]
-
+; CHECK: msr OSLAR_EL1, x3 ; encoding: [0x83,0x10,0x10,0xd5]
+; CHECK: msr DBGDTRTX_EL0, x3 ; encoding: [0x03,0x05,0x13,0xd5]
+
mrs x0, ID_PFR0_EL1
mrs x0, ID_PFR1_EL1
mrs x0, ID_DFR0_EL1
diff --git a/test/MC/ARM64/tls-modifiers-darwin.s b/test/MC/ARM64/tls-modifiers-darwin.s
index 6478d26..8ff07cd 100644
--- a/test/MC/ARM64/tls-modifiers-darwin.s
+++ b/test/MC/ARM64/tls-modifiers-darwin.s
@@ -3,10 +3,10 @@
adrp x2, _var at TLVPPAGE
ldr x0, [x15, _var at TLVPPAGEOFF]
- add lr, x0, _var at TLVPPAGEOFF
+ add x30, x0, _var at TLVPPAGEOFF
; CHECK: adrp x2, _var at TLVPPAG
; CHECK: ldr x0, [x15, _var at TLVPPAGEOFF]
-; CHECK: add lr, x0, _var at TLVPPAGEOFF
+; CHECK: add x30, x0, _var at TLVPPAGEOFF
; CHECK-OBJ: 8 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var
; CHECK-OBJ: 4 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var
diff --git a/test/MC/ARM64/tls-relocs.s b/test/MC/ARM64/tls-relocs.s
index 7e8b754..acb30d9 100644
--- a/test/MC/ARM64/tls-relocs.s
+++ b/test/MC/ARM64/tls-relocs.s
@@ -119,9 +119,9 @@
ldrb w29, [x30, #:tprel_lo12:var]
ldrsb x29, [x28, #:tprel_lo12_nc:var]
-// CHECK: ldrb w29, [lr, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
+// CHECK: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
-// CHECK: ldrsb fp, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]]
@@ -243,9 +243,9 @@
ldrb w29, [x30, #:dtprel_lo12:var]
ldrsb x29, [x28, #:dtprel_lo12_nc:var]
-// CHECK: ldrb w29, [lr, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
+// CHECK: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
-// CHECK: ldrsb fp, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]]
diff --git a/test/MC/ARM64/vector-lists.s b/test/MC/ARM64/vector-lists.s
new file mode 100644
index 0000000..e4cef61
--- /dev/null
+++ b/test/MC/ARM64/vector-lists.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+ ST4 {v0.8B-v3.8B}, [x0]
+ ST4 {v0.4H-v3.4H}, [x0]
+
+// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c]
+// CHECK: st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0] // encoding: [0x00,0x04,0x00,0x0c]
+
+ ST4 {v0.8B-v4.8B}, [x0]
+ ST4 {v0.8B-v3.8B,v4.8B}, [x0]
+ ST4 {v0.8B-v3.8H}, [x0]
+ ST4 {v0.8B-v3.16B}, [x0]
+ ST4 {v0.8B-},[x0]
+
+// CHECK-ERRORS: error: invalid number of vectors
+// CHECK-ERRORS: error: unexpected token in argument list
+// CHECK-ERRORS: error: mismatched register size suffix
+// CHECK-ERRORS: error: mismatched register size suffix
+// CHECK-ERRORS: error: vector register expected
diff --git a/test/MC/ARM64/verbose-vector-case.s b/test/MC/ARM64/verbose-vector-case.s
new file mode 100644
index 0000000..bd36380
--- /dev/null
+++ b/test/MC/ARM64/verbose-vector-case.s
@@ -0,0 +1,19 @@
+// RUN: llvm-mc -triple arm64 -show-encoding < %s | FileCheck %s
+
+pmull v8.8h, v8.8b, v8.8b
+pmull2 v8.8h, v8.16b, v8.16b
+pmull v8.1q, v8.1d, v8.1d
+pmull2 v8.1q, v8.2d, v8.2d
+// CHECK: pmull v8.8h, v8.8b, v8.8b // encoding: [0x08,0xe1,0x28,0x0e]
+// CHECK: pmull2 v8.8h, v8.16b, v8.16b // encoding: [0x08,0xe1,0x28,0x4e]
+// CHECK: pmull v8.1q, v8.1d, v8.1d // encoding: [0x08,0xe1,0xe8,0x0e]
+// CHECK: pmull2 v8.1q, v8.2d, v8.2d // encoding: [0x08,0xe1,0xe8,0x4e]
+
+pmull v8.8H, v8.8B, v8.8B
+pmull2 v8.8H, v8.16B, v8.16B
+pmull v8.1Q, v8.1D, v8.1D
+pmull2 v8.1Q, v8.2D, v8.2D
+// CHECK: pmull v8.8h, v8.8b, v8.8b // encoding: [0x08,0xe1,0x28,0x0e]
+// CHECK: pmull2 v8.8h, v8.16b, v8.16b // encoding: [0x08,0xe1,0x28,0x4e]
+// CHECK: pmull v8.1q, v8.1d, v8.1d // encoding: [0x08,0xe1,0xe8,0x0e]
+// CHECK: pmull2 v8.1q, v8.2d, v8.2d // encoding: [0x08,0xe1,0xe8,0x4e]
diff --git a/test/MC/Disassembler/ARM64/advsimd.txt b/test/MC/Disassembler/ARM64/advsimd.txt
index 486dd16..a943aec 100644
--- a/test/MC/Disassembler/ARM64/advsimd.txt
+++ b/test/MC/Disassembler/ARM64/advsimd.txt
@@ -618,6 +618,7 @@
0x0a 0x68 0x40 0x4c
0x2d 0xac 0x40 0x0c
0x4f 0x7c 0x40 0x4c
+0xe0 0x03 0x40 0x0d
# CHECK: ld1.8b { v1 }, [x1]
# CHECK: ld1.16b { v2, v3 }, [x2]
@@ -627,6 +628,7 @@
# CHECK: ld1.4s { v10, v11, v12 }, [x0]
# CHECK: ld1.1d { v13, v14 }, [x1]
# CHECK: ld1.2d { v15 }, [x2]
+# CHECK: ld1.b { v0 }[0], [sp]
0x41 0x70 0xdf 0x0c
0x41 0xa0 0xdf 0x0c
diff --git a/test/MC/Disassembler/ARM64/arithmetic.txt b/test/MC/Disassembler/ARM64/arithmetic.txt
index 3981219..d68f43b 100644
--- a/test/MC/Disassembler/ARM64/arithmetic.txt
+++ b/test/MC/Disassembler/ARM64/arithmetic.txt
@@ -49,11 +49,13 @@
0x83 0x00 0x50 0x31
0x83 0x00 0x10 0xb1
0x83 0x00 0x50 0xb1
+0xff 0x83 0x00 0xb1
# CHECK: adds w3, w4, #1024
# CHECK: adds w3, w4, #4194304
# CHECK: adds x3, x4, #1024
# CHECK: adds x3, x4, #4194304
+# CHECK: cmn sp, #32
0x83 0x00 0x10 0x51
0x83 0x00 0x50 0x51
@@ -71,11 +73,13 @@
0x83 0x00 0x50 0x71
0x83 0x00 0x10 0xf1
0x83 0x00 0x50 0xf1
+0xff 0x83 0x00 0xf1
# CHECK: subs w3, w4, #1024
# CHECK: subs w3, w4, #4194304
# CHECK: subs x3, x4, #1024
# CHECK: subs x3, x4, #4194304
+# CHECK: cmp sp, #32
#==---------------------------------------------------------------------------==
# Add/Subtract register with (optional) shift
@@ -85,72 +89,72 @@
0xac 0x01 0x0e 0x8b
0xac 0x31 0x0e 0x0b
0xac 0x31 0x0e 0x8b
-0xac 0xa9 0x4e 0x0b
-0xac 0xa9 0x4e 0x8b
-0xac 0x9d 0x8e 0x0b
+0xac 0x29 0x4e 0x0b
+0xac 0x29 0x4e 0x8b
+0xac 0x1d 0x8e 0x0b
0xac 0x9d 0x8e 0x8b
# CHECK: add w12, w13, w14
# CHECK: add x12, x13, x14
# CHECK: add w12, w13, w14, lsl #12
# CHECK: add x12, x13, x14, lsl #12
-# CHECK: add w12, w13, w14, lsr #42
-# CHECK: add x12, x13, x14, lsr #42
-# CHECK: add w12, w13, w14, asr #39
+# CHECK: add w12, w13, w14, lsr #10
+# CHECK: add x12, x13, x14, lsr #10
+# CHECK: add w12, w13, w14, asr #7
# CHECK: add x12, x13, x14, asr #39
0xac 0x01 0x0e 0x4b
0xac 0x01 0x0e 0xcb
0xac 0x31 0x0e 0x4b
0xac 0x31 0x0e 0xcb
-0xac 0xa9 0x4e 0x4b
-0xac 0xa9 0x4e 0xcb
-0xac 0x9d 0x8e 0x4b
+0xac 0x29 0x4e 0x4b
+0xac 0x29 0x4e 0xcb
+0xac 0x1d 0x8e 0x4b
0xac 0x9d 0x8e 0xcb
# CHECK: sub w12, w13, w14
# CHECK: sub x12, x13, x14
# CHECK: sub w12, w13, w14, lsl #12
# CHECK: sub x12, x13, x14, lsl #12
-# CHECK: sub w12, w13, w14, lsr #42
-# CHECK: sub x12, x13, x14, lsr #42
-# CHECK: sub w12, w13, w14, asr #39
+# CHECK: sub w12, w13, w14, lsr #10
+# CHECK: sub x12, x13, x14, lsr #10
+# CHECK: sub w12, w13, w14, asr #7
# CHECK: sub x12, x13, x14, asr #39
0xac 0x01 0x0e 0x2b
0xac 0x01 0x0e 0xab
0xac 0x31 0x0e 0x2b
0xac 0x31 0x0e 0xab
-0xac 0xa9 0x4e 0x2b
-0xac 0xa9 0x4e 0xab
-0xac 0x9d 0x8e 0x2b
+0xac 0x29 0x4e 0x2b
+0xac 0x29 0x4e 0xab
+0xac 0x1d 0x8e 0x2b
0xac 0x9d 0x8e 0xab
# CHECK: adds w12, w13, w14
# CHECK: adds x12, x13, x14
# CHECK: adds w12, w13, w14, lsl #12
# CHECK: adds x12, x13, x14, lsl #12
-# CHECK: adds w12, w13, w14, lsr #42
-# CHECK: adds x12, x13, x14, lsr #42
-# CHECK: adds w12, w13, w14, asr #39
+# CHECK: adds w12, w13, w14, lsr #10
+# CHECK: adds x12, x13, x14, lsr #10
+# CHECK: adds w12, w13, w14, asr #7
# CHECK: adds x12, x13, x14, asr #39
0xac 0x01 0x0e 0x6b
0xac 0x01 0x0e 0xeb
0xac 0x31 0x0e 0x6b
0xac 0x31 0x0e 0xeb
-0xac 0xa9 0x4e 0x6b
-0xac 0xa9 0x4e 0xeb
-0xac 0x9d 0x8e 0x6b
+0xac 0x29 0x4e 0x6b
+0xac 0x29 0x4e 0xeb
+0xac 0x1d 0x8e 0x6b
0xac 0x9d 0x8e 0xeb
# CHECK: subs w12, w13, w14
# CHECK: subs x12, x13, x14
# CHECK: subs w12, w13, w14, lsl #12
# CHECK: subs x12, x13, x14, lsl #12
-# CHECK: subs w12, w13, w14, lsr #42
-# CHECK: subs x12, x13, x14, lsr #42
-# CHECK: subs w12, w13, w14, asr #39
+# CHECK: subs w12, w13, w14, lsr #10
+# CHECK: subs x12, x13, x14, lsr #10
+# CHECK: subs w12, w13, w14, asr #7
# CHECK: subs x12, x13, x14, asr #39
#==---------------------------------------------------------------------------==
diff --git a/test/MC/Disassembler/ARM64/basic-a64-undefined.txt b/test/MC/Disassembler/ARM64/basic-a64-undefined.txt
new file mode 100644
index 0000000..0e15af6
--- /dev/null
+++ b/test/MC/Disassembler/ARM64/basic-a64-undefined.txt
@@ -0,0 +1,31 @@
+# These spawn another process so they're rather expensive. Not many.
+
+# LDR/STR: undefined if option field is 10x or 00x.
+# RUN: echo "0x00 0x08 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0x00 0x88 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
+
+# Instructions notionally in the add/sub (extended register) sheet, but with
+# invalid shift amount or "opt" field.
+# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+
+# MOVK with sf == 0 and hw<1> == 1 is unallocated.
+# RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+
+# ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
+# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+
+# UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
+# RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+
+# EXT on vectors of i8 must have imm<3> = 0.
+# RUN: echo "0x00 0x40 0x00 0x2e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+
+# SCVTF on fixed point W-registers is undefined if scale<5> == 0.
+# Same with FCVTZS and FCVTZU.
+# RUN: echo "0x00 0x00 0x02 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0x00 0x00 0x18 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+
+# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM64/canonical-form.txt b/test/MC/Disassembler/ARM64/canonical-form.txt
new file mode 100644
index 0000000..09467a3
--- /dev/null
+++ b/test/MC/Disassembler/ARM64/canonical-form.txt
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
+
+0x00 0x08 0x00 0xc8
+
+# CHECK: stxr w0, x0, [x0]
+
+0x00 0x00 0x40 0x9b
+
+# CHECK: smulh x0, x0, x0
+
+0x08 0x20 0x21 0x1e
+
+# CHECK: fcmp s0, #0.0
+
+0x1f 0x00 0x00 0x11
+
+# CHECK: mov wsp, w0
+
+0x00 0x7c 0x00 0x13
+
+# CHECK: asr w0, w0, #0
diff --git a/test/MC/Disassembler/ARM64/logical.txt b/test/MC/Disassembler/ARM64/logical.txt
index 29db8cb..e3cb3eb 100644
--- a/test/MC/Disassembler/ARM64/logical.txt
+++ b/test/MC/Disassembler/ARM64/logical.txt
@@ -13,6 +13,7 @@
0x00 0x00 0x40 0xf2
0x41 0x0c 0x00 0x72
0x41 0x0c 0x40 0xf2
+0x5f 0x0c 0x40 0xf2
# CHECK: and w0, w0, #0x1
# CHECK: and x0, x0, #0x1
@@ -23,18 +24,23 @@
# CHECK: ands x0, x0, #0x1
# CHECK: ands w1, w2, #0xf
# CHECK: ands x1, x2, #0xf
+# CHECK: tst x2, #0xf
0x41 0x00 0x12 0x52
0x41 0x00 0x71 0xd2
+0x5f 0x00 0x71 0xd2
# CHECK: eor w1, w2, #0x4000
# CHECK: eor x1, x2, #0x8000
+# CHECK: eor sp, x2, #0x8000
0x41 0x00 0x12 0x32
0x41 0x00 0x71 0xb2
+0x5f 0x00 0x71 0xb2
# CHECK: orr w1, w2, #0x4000
# CHECK: orr x1, x2, #0x8000
+# CHECK: orr sp, x2, #0x8000
#==---------------------------------------------------------------------------==
# 5.5.3 Logical (shifted register)
diff --git a/test/MC/Disassembler/ARM64/memory.txt b/test/MC/Disassembler/ARM64/memory.txt
index 031bfa6..54556a1 100644
--- a/test/MC/Disassembler/ARM64/memory.txt
+++ b/test/MC/Disassembler/ARM64/memory.txt
@@ -83,6 +83,8 @@
0x64 0x00 0x00 0x39
0x85 0x50 0x00 0x39
0xe2 0x43 0x00 0x79
+ 0x00 0xe8 0x20 0x38
+ 0x00 0x48 0x20 0x38
# CHECK: str x4, [x3]
# CHECK: str x2, [sp, #32]
@@ -95,6 +97,8 @@
# CHECK: strb w4, [x3]
# CHECK: strb w5, [x4, #20]
# CHECK: strh w2, [sp, #32]
+# CHECK: strb w0, [x0, x0, sxtx]
+# CHECK: strb w0, [x0, w0, uxtw]
#-----------------------------------------------------------------------------
# Unscaled immediate loads and stores
@@ -210,8 +214,8 @@
0x08 0x8c 0x40 0xfc
0x09 0x0c 0xc1 0x3c
-# CHECK: ldr fp, [x7, #8]!
-# CHECK: ldr lr, [x7, #8]!
+# CHECK: ldr x29, [x7, #8]!
+# CHECK: ldr x30, [x7, #8]!
# CHECK: ldr b5, [x0, #1]!
# CHECK: ldr h6, [x0, #2]!
# CHECK: ldr s7, [x0, #4]!
@@ -226,8 +230,8 @@
0x08 0x8c 0x1f 0xfc
0x09 0x0c 0x9f 0x3c
-# CHECK: str lr, [x7, #-8]!
-# CHECK: str fp, [x7, #-8]!
+# CHECK: str x30, [x7, #-8]!
+# CHECK: str x29, [x7, #-8]!
# CHECK: str b5, [x0, #-1]!
# CHECK: str h6, [x0, #-2]!
# CHECK: str s7, [x0, #-4]!
@@ -246,8 +250,8 @@
0x08 0x84 0x1f 0xfc
0x09 0x04 0x9f 0x3c
-# CHECK: str lr, [x7], #-8
-# CHECK: str fp, [x7], #-8
+# CHECK: str x30, [x7], #-8
+# CHECK: str x29, [x7], #-8
# CHECK: str b5, [x0], #-1
# CHECK: str h6, [x0], #-2
# CHECK: str s7, [x0], #-4
@@ -262,8 +266,8 @@
0x08 0x84 0x40 0xfc
0x09 0x04 0xc1 0x3c
-# CHECK: ldr fp, [x7], #8
-# CHECK: ldr lr, [x7], #8
+# CHECK: ldr x29, [x7], #8
+# CHECK: ldr x30, [x7], #8
# CHECK: ldr b5, [x0], #1
# CHECK: ldr h6, [x0], #2
# CHECK: ldr s7, [x0], #4
@@ -416,15 +420,17 @@
# CHECK: ldr q1, [x1, x2]
# CHECK: ldr q1, [x1, x2, lsl #4]
+ 0x00 0x48 0x20 0x7c
0xe1 0x6b 0x23 0xfc
0xe1 0x5b 0x23 0xfc
0xe1 0x6b 0xa3 0x3c
0xe1 0x5b 0xa3 0x3c
+# CHECK: str h0, [x0, w0, uxtw]
# CHECK: str d1, [sp, x3]
-# CHECK: str d1, [sp, x3, uxtw #3]
+# CHECK: str d1, [sp, w3, uxtw #3]
# CHECK: str q1, [sp, x3]
-# CHECK: str q1, [sp, x3, uxtw #4]
+# CHECK: str q1, [sp, w3, uxtw #4]
#-----------------------------------------------------------------------------
# Load/Store exclusive
diff --git a/test/MC/Disassembler/ARM64/non-apple-fmov.txt b/test/MC/Disassembler/ARM64/non-apple-fmov.txt
new file mode 100644
index 0000000..e3c3a99
--- /dev/null
+++ b/test/MC/Disassembler/ARM64/non-apple-fmov.txt
@@ -0,0 +1,7 @@
+# RUN: llvm-mc -triple arm64 -disassemble < %s | FileCheck %s
+
+0x00 0x00 0xae 0x9e
+0x00 0x00 0xaf 0x9e
+
+# CHECK: fmov x0, v0.d[1]
+# CHECK: fmov v0.d[1], x0
diff --git a/test/MC/Disassembler/ARM64/scalar-fp.txt b/test/MC/Disassembler/ARM64/scalar-fp.txt
index b242df5..732e1c1 100644
--- a/test/MC/Disassembler/ARM64/scalar-fp.txt
+++ b/test/MC/Disassembler/ARM64/scalar-fp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple arm64-apple-darwin --disassemble -output-asm-variant=1 < %s | FileCheck %s
#-----------------------------------------------------------------------------
# Floating-point arithmetic
diff --git a/test/MC/Disassembler/ARM64/system.txt b/test/MC/Disassembler/ARM64/system.txt
index cefa635..9027a60 100644
--- a/test/MC/Disassembler/ARM64/system.txt
+++ b/test/MC/Disassembler/ARM64/system.txt
@@ -26,10 +26,14 @@
# CHECK: clrex #10
0xdf 0x3f 0x03 0xd5
# CHECK: isb{{$}}
+ 0xdf 0x31 0x03 0xd5
+# CHECK: isb #1
0xbf 0x33 0x03 0xd5
# CHECK: dmb osh
0x9f 0x37 0x03 0xd5
# CHECK: dsb nsh
+ 0x3f 0x76 0x08 0xd5
+# CHECK: dc ivac
#-----------------------------------------------------------------------------
# Generic system instructions
@@ -38,19 +42,19 @@
0xe7 0x6a 0x0f 0xd5
0xf4 0x3f 0x2e 0xd5
0xbf 0x40 0x00 0xd5
- 0x00 0x00 0x10 0xd5
- 0x00 0x00 0x30 0xd5
+ 0x00 0xb0 0x18 0xd5
+ 0x00 0xb0 0x38 0xd5
# CHECK: sys #2, c0, c5, #7
# CHECK: sys #7, c6, c10, #7, x7
# CHECK: sysl x20, #6, c3, c15, #7
-# CHECK: msr SPSel, #0
-# CHECK: msr S2_0_C0_C0_0, x0
-# CHECK: mrs x0, S2_0_C0_C0_0
+# CHECK: msr SPSEL, #0
+# CHECK: msr S3_0_C11_C0_0, x0
+# CHECK: mrs x0, S3_0_C11_C0_0
0x40 0xc0 0x1e 0xd5
- 0x40 0xc0 0x1a 0xd5
- 0x40 0xc0 0x19 0xd5
+ 0x40 0xc0 0x1c 0xd5
+ 0x40 0xc0 0x18 0xd5
# CHECK: msr RMR_EL3, x0
# CHECK: msr RMR_EL2, x0
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