<div dir="ltr"><p>Hi Tim (and other reviewers),</p><p>As discussed at Euro-LLVM and offline, we (Bradley and I) have been working for a week on getting ARM's internal "MC Hammer" test suite passing on the ARM64 backend. With the attached patches, ARM64 is fully correct when<br>
comparing with our "golden reference" implementation, same as AArch64, with the exception of:</p><p>  * SXTB/UXTB will erroneously accept operands that are invalid. For example, they will accept X registers when they shouldn't.<br>
  * A cyclone specific system register is not understood by our golden reference.</p><p>We have done point fixes on a bunch of InstAliases, but actually we think the alias logic should be refactored so that it is in one place instead of 4 (instprinter,asmparser,disassembler,tblgen).</p>
<p>I apologise that there are so many patches attached, but most are very small. I've also attached a monolithic patch for your convenience. There are a ton of small fixes and one fairly large refactor which brings over the<br>
system register implementation from AArch64 to ARM64.</p><p>Patch list, in descending size order:<br>222K 0010-ARM64-Move-ARM64BaseInfo.-cpp-h-into-a-Utils-subdire.patch<br> 73K 0009-ARM64-Copy-the-named-immediate-operand-mapping-logic.patch<br>
 44K 0011-ARM64-Switch-the-decoder-disassembler-instprinter-an.patch<br> 24K 0013-ARM64-Remove-ARM64SYS.patch<br> 21K 0027-ARM64-Rename-FP-to-the-UAL-compliant-X29.patch<br> 14K 0019-ARM64-Add-missing-tlbi-operands-and-error-for-extra-.patch<br>
 14K 0018-ARM64-Rework-system-register-parsing-to-overcome-SPS.patch<br> 12K 0028-ARM64-Rename-LR-to-the-UAL-compliant-X30.patch<br> 11K 0021-ARM64-Floating-point-to-fixed-point-scaled-conversio.patch<br> 10K 0031-ARM64-Fixup-ADR-ADRP-parsing-such-that-they-accept-i.patch<br>
9.4K 0035-ARM64-When-printing-a-pre-indexed-address-with-0-the.patch<br>9.4K 0032-ARM64-Fix-canonicalisation-of-MOVs.-MOV-is-too-compl.patch<br>8.2K 0012-ARM64-Move-CPSRField-and-DBarrier-operands-over-to-A.patch<br>6.0K 0008-ARM64-Shifted-register-ALU-ops-are-reserved-if-sf-0-.patch<br>
6.0K 0015-ARM64-Remove-PrefetchOp-and-use-ARM64PRFM-instead.patch<br>5.8K 0005-ARM64-Add-parsing-for-vector-lists-such-as-v0.8b-v3..patch<br>5.4K 0025-ARM64-SCVTF-and-FCVTZS-U-are-undefined-if-scale-5-0.patch<br>5.4K 0007-ARM64-Add-support-for-NV-condition-code-exists-only-.patch<br>
4.8K 0017-ARM64-Port-over-the-PostEncoderMethod-from-AArch64-f.patch<br>4.3K 0039-ARM64-Properly-support-both-apple-and-standard-synta.patch<br>4.3K 0038-ARM64-Flag-setting-logical-add-sub-immediate-instruc.patch<br>4.1K 0042-ARM64-Change-SYS-without-a-register-to-an-alias-to-m.patch<br>
3.9K 0004-ARM64-Correctly-alias-LSL-to-UXTW-for-32bit-instruct.patch<br>3.9K 0001-ARM64-Register-offset-loads-and-stores-with-the-opti.patch<br>3.8K 0014-ARM64-Add-WZR-to-isGPR32Register-since-every-use-nee.patch<br>3.2K 0029-ARM64-Tighten-up-the-special-casing-in-emitting-arit.patch<br>
3.0K 0020-ARM64-Port-over-the-PostEncoderMethod-fix-for-SMULH-.patch<br>2.9K 0034-ARM64-Add-missing-shifted-register-MVN-alias-to-ORN.patch<br>2.8K 0026-ARM64-Add-a-PostEncoderMethod-to-FCMP-the-Rm-field-s.patch<br>2.6K 0002-ARM64-MOVK-with-sf-0-and-hw-1-1-is-unallocated.-Shif.patch<br>
2.3K 0036-ARM64-Fix-disassembly-logic-for-extended-loads-store.patch<br>2.1K 0006-ARM64-Add-missing-1Q-1q-vector-kind-alias.patch<br>2.1K 0022-ARM64-UBFM-BFM-is-undefined-on-w-registers-when-imms.patch<br>2.0K 0024-ARM64-EXT-and-EXTR-instructions-on-v8i8-and-W-regs-r.patch<br>
1.9K 0030-ARM64-Ensure-sp-is-decoded-as-SP-not-XZR-in-LD1-inst.patch<br>1.8K 0041-ARM64-Correctly-disassemble-ISB-operand-as-ISB-not-D.patch<br>1.7K 0037-ARM64-Conditional-branches-must-always-print-their-c.patch<br>1.6K 0003-ARM64-STRHro-and-STRBro-were-not-being-decoded-at-al.patch<br>
1.5K 0033-ARM64-SXTW-UXTW-are-only-valid-aliases-for-32-bit-op.patch<br>1.3K 0016-ARM64-Use-PStateMapper-to-ensure-that-MSRcpsr-operan.patch<br> 834 0023-ARM64-Scaled-fixed-point-FCVTZSs-should-also-have-bi.patch</p><p>Cheers,</p>
<p>James (and Bradley)<br></p></div>