[llvm] r205222 - [PowerPC] Correct P7 dispatch unit allocation for vector instructions
Hal Finkel
hfinkel at anl.gov
Mon Mar 31 10:02:11 PDT 2014
Author: hfinkel
Date: Mon Mar 31 12:02:10 2014
New Revision: 205222
URL: http://llvm.org/viewvc/llvm-project?rev=205222&view=rev
Log:
[PowerPC] Correct P7 dispatch unit allocation for vector instructions
Modified:
llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td?rev=205222&r1=205221&r2=205222&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td Mon Mar 31 12:02:10 2014
@@ -339,36 +339,28 @@ def P7Itineraries : ProcessorItineraries
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[5, 1, 1]>,
- InstrItinData<IIC_VecGeneral , [InstrStage<1, [P7_DU1, P7_DU2,
- P7_DU3, P7_DU4], 0>,
+ InstrItinData<IIC_VecGeneral , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_VS1]>],
[2, 1, 1]>,
- InstrItinData<IIC_VecVSL , [InstrStage<1, [P7_DU1, P7_DU2,
- P7_DU3, P7_DU4], 0>,
+ InstrItinData<IIC_VecVSL , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_VS1]>],
[2, 1, 1]>,
- InstrItinData<IIC_VecVSR , [InstrStage<1, [P7_DU1, P7_DU2,
- P7_DU3, P7_DU4], 0>,
+ InstrItinData<IIC_VecVSR , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_VS1]>],
[2, 1, 1]>,
- InstrItinData<IIC_VecFP , [InstrStage<1, [P7_DU1, P7_DU2,
- P7_DU3, P7_DU4], 0>,
+ InstrItinData<IIC_VecFP , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[6, 1, 1]>,
- InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1, P7_DU2,
- P7_DU3, P7_DU4], 0>,
+ InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[6, 1, 1]>,
- InstrItinData<IIC_VecFPRound , [InstrStage<1, [P7_DU1, P7_DU2,
- P7_DU3, P7_DU4], 0>,
+ InstrItinData<IIC_VecFPRound , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>],
[6, 1, 1]>,
- InstrItinData<IIC_VecComplex , [InstrStage<1, [P7_DU1, P7_DU2,
- P7_DU3, P7_DU4], 0>,
+ InstrItinData<IIC_VecComplex , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_VS1]>],
[7, 1, 1]>,
- InstrItinData<IIC_VecPerm , [InstrStage<1, [P7_DU1, P7_DU2,
- P7_DU3, P7_DU4], 0>,
+ InstrItinData<IIC_VecPerm , [InstrStage<1, [P7_DU1, P7_DU2], 0>,
InstrStage<1, [P7_VS2]>],
[3, 1, 1]>
]>;
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