[PATCH] Adds Cortex-A53 and Cortex-A57 subtargets.

[Dave Estes]

Hi apazos, mcrosier, atrick,

This is a work in progress to provide a machine description for the
Cortex-A53 subtarget in the AArch64 backend.

This patch lays the ground work to annotate each AArch64 instruction
(no NEON yet) with a list of SchedReadWrite types. The patch also
provides the Cortex-A53 processor resources, maps those the the default
SchedReadWrites, and provides basic latency. NEON support will be added
in a subsequent patch with proper forwarding logic soon the likely next
patch.

Verification was doneg by setting the pre-RA scheduler to linearize to
better gauge the effect of the MIScheduler. Even without modeling the
forward logic, the results show a modest improvement for Cortex-A53.

http://llvm-reviews.chandlerc.com/D2829

Files:
  lib/Target/AArch64/AArch64.td
  lib/Target/AArch64/AArch64InstrInfo.td
  lib/Target/AArch64/AArch64Schedule.td
  lib/Target/AArch64/AArch64ScheduleA53.td
  lib/Target/AArch64/AArch64Subtarget.h
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D2829.1.patch
Type: text/x-patch
Size: 74645 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20140219/871735f1/attachment.bin>