[PATCH] [AArch64]Add code to copy FPR8 in CopyPhysReg

[Jiangning Liu]

LGTM!

One point is uqadd should be commutable, so in theory fmov can be optimized
away.

Thanks,
-Jiangning


2014-01-24 17:57 GMT+08:00 Hao Liu <Hao.Liu at arm.com>:

> Hi t.p.northover,
>
> Hi Tim and reviewers,
>
> This patch add code to copy FPR8 in CopyPhysReg(). The implementation is
> like FPR16 and FPR32 by using FMOV.
>
> Review, please.
>
> Thanks,
> -Hao
>
> http://llvm-reviews.chandlerc.com/D2611
>
> Files:
>   lib/Target/AArch64/AArch64InstrInfo.cpp
>   test/CodeGen/AArch64/neon-copy.ll
>
> Index: lib/Target/AArch64/AArch64InstrInfo.cpp
> ===================================================================
> --- lib/Target/AArch64/AArch64InstrInfo.cpp
> +++ lib/Target/AArch64/AArch64InstrInfo.cpp
> @@ -142,6 +142,16 @@
>      BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)
>        .addReg(Src);
>      return;
> +  } else if (AArch64::FPR8RegClass.contains(DestReg, SrcReg)) {
> +    // The copy of two FPR8 registers is implemented by the copy of two
> FPR32
> +    const TargetRegisterInfo *TRI = &getRegisterInfo();
> +    unsigned Dst = TRI->getMatchingSuperReg(DestReg, AArch64::sub_8,
> +                                            &AArch64::FPR32RegClass);
> +    unsigned Src = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_8,
> +                                            &AArch64::FPR32RegClass);
> +    BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)
> +      .addReg(Src);
> +    return;
>    } else {
>      CopyPhysRegTuple(MBB, I, DL, DestReg, SrcReg);
>      return;
> Index: test/CodeGen/AArch64/neon-copy.ll
> ===================================================================
> --- test/CodeGen/AArch64/neon-copy.ll
> +++ test/CodeGen/AArch64/neon-copy.ll
> @@ -1274,3 +1274,14 @@
>    %vsqadd2.i = call <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16>
> %b, <1 x i16> %a)
>    ret <1 x i16> %vsqadd2.i
>  }
> +
> +define <1 x i8> @test_copy_FPR8_FPR8(<1 x i8> %a, <1 x i8> %b) {
> +; CHECK-LABEL: test_copy_FPR8_FPR8:
> +; CHECK: usqadd b1, b0
> +; CHECK-NEXT: fmov s0, s1
> +entry:
> + %vsqadd2.i = call <1 x i8> @llvm.aarch64.neon.vsqadd.v1i8(<1 x i8> %b,
> <1 x i8> %a)
> + ret <1 x i8> %vsqadd2.i
> +}
> +
> +declare <1 x i8> @llvm.aarch64.neon.vsqadd.v1i8(<1 x i8>, <1 x i8>)
>
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>


-- 
Thanks,
-Jiangning
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