<div dir="ltr"><div class="gmail_default" style="font-family:arial,helvetica,sans-serif;font-size:small">LGTM!</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif;font-size:small"><br></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif;font-size:small">
One point is uqadd should be commutable, so in theory fmov can be optimized away.</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif;font-size:small"><br></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif;font-size:small">
Thanks,</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif;font-size:small">-Jiangning</div></div><div class="gmail_extra"><br><br><div class="gmail_quote">2014-01-24 17:57 GMT+08:00 Hao Liu <span dir="ltr"><<a href="mailto:Hao.Liu@arm.com" target="_blank">Hao.Liu@arm.com</a>></span>:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi t.p.northover,<br>
<br>
Hi Tim and reviewers,<br>
<br>
This patch add code to copy FPR8 in CopyPhysReg(). The implementation is like FPR16 and FPR32 by using FMOV.<br>
<br>
Review, please.<br>
<br>
Thanks,<br>
-Hao<br>
<br>
<a href="http://llvm-reviews.chandlerc.com/D2611" target="_blank">http://llvm-reviews.chandlerc.com/D2611</a><br>
<br>
Files:<br>
lib/Target/AArch64/AArch64InstrInfo.cpp<br>
test/CodeGen/AArch64/neon-copy.ll<br>
<br>
Index: lib/Target/AArch64/AArch64InstrInfo.cpp<br>
===================================================================<br>
--- lib/Target/AArch64/AArch64InstrInfo.cpp<br>
+++ lib/Target/AArch64/AArch64InstrInfo.cpp<br>
@@ -142,6 +142,16 @@<br>
BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)<br>
.addReg(Src);<br>
return;<br>
+ } else if (AArch64::FPR8RegClass.contains(DestReg, SrcReg)) {<br>
+ // The copy of two FPR8 registers is implemented by the copy of two FPR32<br>
+ const TargetRegisterInfo *TRI = &getRegisterInfo();<br>
+ unsigned Dst = TRI->getMatchingSuperReg(DestReg, AArch64::sub_8,<br>
+ &AArch64::FPR32RegClass);<br>
+ unsigned Src = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_8,<br>
+ &AArch64::FPR32RegClass);<br>
+ BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)<br>
+ .addReg(Src);<br>
+ return;<br>
} else {<br>
CopyPhysRegTuple(MBB, I, DL, DestReg, SrcReg);<br>
return;<br>
Index: test/CodeGen/AArch64/neon-copy.ll<br>
===================================================================<br>
--- test/CodeGen/AArch64/neon-copy.ll<br>
+++ test/CodeGen/AArch64/neon-copy.ll<br>
@@ -1274,3 +1274,14 @@<br>
%vsqadd2.i = call <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16> %b, <1 x i16> %a)<br>
ret <1 x i16> %vsqadd2.i<br>
}<br>
+<br>
+define <1 x i8> @test_copy_FPR8_FPR8(<1 x i8> %a, <1 x i8> %b) {<br>
+; CHECK-LABEL: test_copy_FPR8_FPR8:<br>
+; CHECK: usqadd b1, b0<br>
+; CHECK-NEXT: fmov s0, s1<br>
+entry:<br>
+ %vsqadd2.i = call <1 x i8> @llvm.aarch64.neon.vsqadd.v1i8(<1 x i8> %b, <1 x i8> %a)<br>
+ ret <1 x i8> %vsqadd2.i<br>
+}<br>
+<br>
+declare <1 x i8> @llvm.aarch64.neon.vsqadd.v1i8(<1 x i8>, <1 x i8>)<br>
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<br></blockquote></div><br><br clear="all"><div><br></div>-- <br><div dir="ltr"><font face="courier new, monospace">Thanks,</font><div><font face="courier new, monospace">-Jiangning</font></div></div>
</div>