[PATCH] Forbid the use of registers t6, t7 and t8 if the target is MIPS NaCl.

[Mark Seaborn]

================
Comment at: lib/Target/Mips/MipsCallingConv.td:198
@@ +197,3 @@
+
+  // In PNaCl, T6, T7 and T8 are reserved and not available as argument
+  // registers for fastcc.
----------------
Nit: should be "NaCl" rather than "PNaCl".  (NaCl is the sandboxing system and PNaCl is the LLVM-based portability layer.)

================
Comment at: lib/Target/Mips/MipsRegisterInfo.cpp:137
@@ -136,1 +136,3 @@
 
+  // Reserved for PNaCl use
+  if (Subtarget.isTargetNaCl()) {
----------------
Eric Christopher wrote:
> Comments should be complete sentences. Also, if you can, you should add what the various registers are used for so that it's documented.
Again, should be "NaCl" rather than "PNaCl"

================
Comment at: test/CodeGen/Mips/nacl-reserved-regs.ll:42
@@ +41,3 @@
+  %16 = load i32* @g16
+  %add = add i32 %1, %0
+  %add1 = add i32 %add, %2
----------------
If this is just calculating a running sum of all g0-g16, it seems like this isn't a robust way to force use of many registers, because the backend can move the adds between the loads so only a couple of registers are used.

Maybe do something like:
%val1 = call i32 @get_val()
...
%valN = call i32 @get_val()
call void @use_val(i32 %val1)
...
call void @use_val(i32 %valN)

Or just do:
call fastcc void @foo(i32 1, ..., i32 16)
to check handling of "fastcc"


================
Comment at: test/CodeGen/Mips/nacl-reserved-regs.ll:66
@@ +65,3 @@
+; t6, t7 and t8 are reserved in PNaCl.
+; CHECK-NACL-NOT: $14
+; CHECK-NACL-NOT: $15
----------------
Also, this is going to start failing when the implementation of NaCl address masking is added to the MIPS backend, because that will use these registers. :-)  So you might want to try running this test against the pnacl-llvm branch too.

Maybe check directly for spill load/store instructions, and for movs that fill out function arguments?


http://llvm-reviews.chandlerc.com/D2694