[llvm] r198758 - [x86] Use 16-bit addressing where possible in 16-bit mode
David Woodhouse
dwmw2 at infradead.org
Wed Jan 8 04:58:19 PST 2014
Author: dwmw2
Date: Wed Jan 8 06:58:18 2014
New Revision: 198758
URL: http://llvm.org/viewvc/llvm-project?rev=198758&view=rev
Log:
[x86] Use 16-bit addressing where possible in 16-bit mode
Where "where possible" means that it's an immediate value and it's below
0x10000. In fact GAS will either truncate or error with larger values,
and will insist on using the addr32 prefix to get 32-bit addressing. So
perhaps we should do that, in a later patch.
Modified:
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/trunk/test/MC/X86/x86-16.s
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=198758&r1=198757&r2=198758&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Wed Jan 8 06:58:18 2014
@@ -57,6 +57,24 @@ public:
return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
}
+ /// Is16BitMemOperand - Return true if the specified instruction has
+ /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
+ bool Is16BitMemOperand(const MCInst &MI, unsigned Op) const {
+ const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
+ const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
+ const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
+
+ if (is16BitMode() && BaseReg.getReg() == 0 &&
+ Disp.isImm() && Disp.getImm() < 0x10000)
+ return true;
+ if ((BaseReg.getReg() != 0 &&
+ X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
+ (IndexReg.getReg() != 0 &&
+ X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
+ return true;
+ return false;
+ }
+
unsigned GetX86RegNum(const MCOperand &MO) const {
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
}
@@ -250,20 +268,6 @@ static bool Is64BitMemOperand(const MCIn
}
#endif
-/// Is16BitMemOperand - Return true if the specified instruction has
-/// a 16-bit memory operand. Op specifies the operand # of the memoperand.
-static bool Is16BitMemOperand(const MCInst &MI, unsigned Op) {
- const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
- const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
-
- if ((BaseReg.getReg() != 0 &&
- X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
- (IndexReg.getReg() != 0 &&
- X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
- return true;
- return false;
-}
-
/// StartsWithGlobalOffsetTable - Check if this expression starts with
/// _GLOBAL_OFFSET_TABLE_ and if it is of the form
/// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
Modified: llvm/trunk/test/MC/X86/x86-16.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-16.s?rev=198758&r1=198757&r2=198758&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-16.s (original)
+++ llvm/trunk/test/MC/X86/x86-16.s Wed Jan 8 06:58:18 2014
@@ -319,6 +319,10 @@ cmovnae %bx,%bx
// CHECK: encoding: [0x9b]
fwait
+// CHECK: [0x65,0x66,0x8b,0x06,0x7c,0x00]
+// FIXME: This is a correct bug poor encoding: Use 65 66 a1 7c 00
+ movl %gs:124, %eax
+
// CHECK: pusha
// CHECK: encoding: [0x60]
pusha
@@ -701,6 +705,54 @@ pshufw $90, %mm4, %mm0
// CHECK: encoding: [0xdf,0xe9]
fucompi
+// CHECK: fldcw 32493
+// CHECK: encoding: [0xd9,0x2e,0xed,0x7e]
+ fldcww 0x7eed
+
+// CHECK: fldcw 32493
+// CHECK: encoding: [0xd9,0x2e,0xed,0x7e]
+ fldcw 0x7eed
+
+// CHECK: fnstcw 32493
+// CHECK: encoding: [0xd9,0x3e,0xed,0x7e]
+ fnstcww 0x7eed
+
+// CHECK: fnstcw 32493
+// CHECK: encoding: [0xd9,0x3e,0xed,0x7e]
+ fnstcw 0x7eed
+
+// CHECK: wait
+// CHECK: encoding: [0x9b]
+ fstcww 0x7eed
+
+// CHECK: wait
+// CHECK: encoding: [0x9b]
+ fstcw 0x7eed
+
+// CHECK: fnstsw 32493
+// CHECK: encoding: [0xdd,0x3e,0xed,0x7e]
+ fnstsww 0x7eed
+
+// CHECK: fnstsw 32493
+// CHECK: encoding: [0xdd,0x3e,0xed,0x7e]
+ fnstsw 0x7eed
+
+// CHECK: wait
+// CHECK: encoding: [0x9b]
+ fstsww 0x7eed
+
+// CHECK: wait
+// CHECK: encoding: [0x9b]
+ fstsw 0x7eed
+
+// CHECK: verr 32493
+// CHECK: encoding: [0x0f,0x00,0x26,0xed,0x7e]
+ verrw 0x7eed
+
+// CHECK: verr 32493
+// CHECK: encoding: [0x0f,0x00,0x26,0xed,0x7e]
+ verr 0x7eed
+
// CHECK: wait
// CHECK: encoding: [0x9b]
fclex
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