[PATCH] [AArch64] Support ISD::SIGN_EXTEND_INREG

[Jiangning Liu]

Hi 
Ana,

Sorry, I don't quite understand what you said. Do you have a small test to
articulate what you mentioned?

For sign_extend_inreg(v2i32, v2i16), my test case below should show my
patch work,

define <2 x i16> @test_sext_inreg_v2i16i32(<2 x i16> %v1, <2 x i16> %v2)
nounwind readnone {
; CHECK-LABEL: test_sext_inreg_v2i16i32
; CHECK: shl     v0.2s, v0.2s, #16
; CHECK: sshr    v0.2s, v0.2s, #16
; CHECK: shl     v1.2s, v1.2s, #16
; CHECK: sshr    v1.2s, v1.2s, #16
  %1 = sext <2 x i16> %v1 to <2 x i32>
  %2 = sext <2 x i16> %v2 to <2 x i32>
  %3 = shufflevector <2 x i32> %1, <2 x i32> %2, <2 x i32> <i32 0, i32 2>
  %4 = trunc <2 x i32> %3 to <2 x i16>
  ret <2 x i16> %4
}

For sign_extend_inreg(v4i16, v8i8), is this a valid? I thought it should be
sign_extend_inreg(v8i16, v8i8). If this is the case, my test below should
also show my patch work,

define <8 x i8> @test_sext_inreg_v8i8i16(<8 x i8> %v1, <8 x i8> %v2)
nounwind readnone {
; CHECK-LABEL: test_sext_inreg_v8i8i16
; CHECK: sshll   v0.8h, v0.8b, #0
; CHECK: sshll   v1.8h, v1.8b, #0
  %1 = sext <8 x i8> %v1 to <8 x i16>
  %2 = sext <8 x i8> %v2 to <8 x i16>
  %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2,
i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
  %4 = trunc <8 x i16> %3 to <8 x i8>
  ret <8 x i8> %4
}

Thanks,
-Jiangning
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