[PATCH] [AArch64] Support ISD::SIGN_EXTEND_INREG

[Ana Pazos]

Hi Jiangning,

 

I happened to be looking at similar sign extend inreg failures.

 

We ran some benchmakrs with -mfpu=neon flag on and noticed failures due to
sign_extend_inreg.

 

For example we see sign_extend_inreg(v2i32, v2i16), sign_extend_inreg(v4i16,
v8i8). Your patch does not catch all  cases.

 

This is what I suggest:

 

-        Loop trough all vector types and setOperationAction to Expand

-        For the vector types we can handle with hardware instruction, do
custom lowering:

o    sign extend inreg for 8H/8B, 4S/4H. 2D/2S can use SXTL (alias to SSHLL
Vd, Vn #0)

o   Sign extend of 8B, 16B, 4H, H, 2S, 4S, 2D can use the combo Shift Lef t+
Shift Right immediate.

 

Do you agree? 

 

Let me know and we can provide the further changes.

 

Ana.

 

From: llvm-commits-bounces at cs.uiuc.edu
[mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Jiangning Liu
Sent: Thursday, January 02, 2014 10:47 PM
To: llvm-commits at cs.uiuc.edu for LLVM
Subject: [PATCH] [AArch64] Support ISD::SIGN_EXTEND_INREG

 

Hi,

 

Attached patch is to lower ISD::SIGN_EXTEND_INREG. Review, please!

 

-- 

Thanks,

-Jiangning

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