[PATCH] Allow 0 offsets to left out for strbt / ldrbt in ARM mode.

[Joerg Sonnenberger]

  Extend to strt/ldrt. Add comments to explain the duplication.

http://llvm-reviews.chandlerc.com/D2510

CHANGE SINCE LAST DIFF
  http://llvm-reviews.chandlerc.com/D2510?vs=6347&id=6348#toc

Files:
  lib/Target/ARM/ARMInstrInfo.td
  test/MC/ARM/arm_addrmode2.s

Index: lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- lib/Target/ARM/ARMInstrInfo.td
+++ lib/Target/ARM/ARMInstrInfo.td
@@ -2460,6 +2460,23 @@
   let DecoderMethod = "DecodeAddrMode2IdxInstruction";
 }
 
+// LDRT_POST_0 should be an alias for LDRT_POST_IMM,
+// but the existing Thumb2 instruction confuses TableGen.
+def LDRT_POST_0 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
+                    (ins addr_offset_none:$addr),
+                   IndexModePost, LdFrm, IIC_iLoad_ru,
+                   "ldrt", "\t$Rt, $addr",
+                   "$addr.base = $Rn_wb", []> {
+  // {12}     isAdd
+  // {11-0}   imm12/Rm
+  bits<4> addr;
+  let Inst{25} = 0;
+  let Inst{23} = 1;
+  let Inst{21} = 1; // overwrite
+  let Inst{19-16} = addr;
+  let Inst{11-0} = 0;
+}
+
 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
                      (ins addr_offset_none:$addr, am2offset_reg:$offset),
                      IndexModePost, LdFrm, IIC_iLoad_bh_ru,
@@ -2496,6 +2513,24 @@
   let DecoderMethod = "DecodeAddrMode2IdxInstruction";
 }
 
+// LDRBT_POST_0 should be an alias for LDRBT_POST_IMM,
+// but the existing Thumb2 instruction confuses TableGen.
+def LDRBT_POST_0 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
+                     (ins addr_offset_none:$addr),
+                    IndexModePost, LdFrm, IIC_iLoad_bh_ru,
+                    "ldrbt", "\t$Rt, $addr",
+                    "$addr.base = $Rn_wb", []> {
+  // {12}     isAdd
+  // {11-0}   imm12/Rm
+  bits<14> offset;
+  bits<4> addr;
+  let Inst{25} = 0;
+  let Inst{23} = 1;
+  let Inst{21} = 1; // overwrite
+  let Inst{19-16} = addr;
+  let Inst{11-0} = 0;
+}
+
 multiclass AI3ldrT<bits<4> op, string opc> {
   def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
                       (ins addr_offset_none:$addr, postidx_imm8:$offset),
@@ -2765,6 +2800,23 @@
   let DecoderMethod = "DecodeAddrMode2IdxInstruction";
 }
 
+// STRBT_POST_0 should be an alias for STRBT_POST_IMM,
+// but the existing Thumb2 instruction confuses TableGen.
+def STRBT_POST_0 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
+                   (ins GPR:$Rt, addr_offset_none:$addr),
+                   IndexModePost, StFrm, IIC_iStore_bh_ru,
+                   "strbt", "\t$Rt, $addr",
+                   "$addr.base = $Rn_wb", []> {
+  // {12}     isAdd
+  // {11-0}   imm12/Rm
+  bits<4> addr;
+  let Inst{25} = 0;
+  let Inst{23} = 1;
+  let Inst{21} = 1; // overwrite
+  let Inst{19-16} = addr;
+  let Inst{11-0} = 0;
+}
+
 let mayStore = 1, neverHasSideEffects = 1 in {
 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
                    (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
@@ -2801,7 +2853,24 @@
   let Inst{11-0} = offset{11-0};
   let DecoderMethod = "DecodeAddrMode2IdxInstruction";
 }
+
+// STRT_POST_0 should be an alias for STRT_POST_IMM,
+// but the existing Thumb2 instruction confuses TableGen.
+def STRT_POST_0 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
+                   (ins GPR:$Rt, addr_offset_none:$addr),
+                   IndexModePost, StFrm, IIC_iStore_ru,
+                   "strt", "\t$Rt, $addr",
+                   "$addr.base = $Rn_wb", []> {
+  // {12}     isAdd
+  // {11-0}   imm12/Rm
+  bits<4> addr;
+  let Inst{25} = 0;
+  let Inst{23} = 1;
+  let Inst{21} = 1; // overwrite
+  let Inst{19-16} = addr;
+  let Inst{11-0} = 0;
 }
+}
 
 
 multiclass AI3strT<bits<4> op, string opc> {
Index: test/MC/ARM/arm_addrmode2.s
===================================================================
--- test/MC/ARM/arm_addrmode2.s
+++ test/MC/ARM/arm_addrmode2.s
@@ -4,27 +4,35 @@
 @ CHECK: ldrt  r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
 @ CHECK: ldrt  r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
 @ CHECK: ldrt  r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
+@ CHECK: ldrt  r1, [r0] @ encoding: [0x00,0x10,0xb0,0xe4]
 @ CHECK: ldrbt  r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
 @ CHECK: ldrbt  r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
 @ CHECK: ldrbt  r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
+@ CHECK: ldrbt  r1, [r0] @ encoding: [0x00,0x10,0xf0,0xe4]
 @ CHECK: strt  r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
 @ CHECK: strt  r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
 @ CHECK: strt  r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]
+@ CHECK: strt  r1, [r0] @ encoding: [0x00,0x10,0xa0,0xe4]
 @ CHECK: strbt  r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6]
 @ CHECK: strbt  r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
 @ CHECK: strbt  r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4]
+@ CHECK: strbt  r1, [r0] @ encoding: [0x00,0x10,0xe0,0xe4]
         ldrt  r1, [r0], r2
         ldrt  r1, [r0], r2, lsr #3
         ldrt  r1, [r0], #4
+        ldrt  r1, [r0]
         ldrbt  r1, [r0], r2
         ldrbt  r1, [r0], r2, lsr #3
         ldrbt  r1, [r0], #4
+        ldrbt  r1, [r0]
         strt  r1, [r0], r2
         strt  r1, [r0], r2, lsr #3
         strt  r1, [r0], #4
+        strt  r1, [r0]
         strbt  r1, [r0], r2
         strbt  r1, [r0], r2, lsr #3
         strbt  r1, [r0], #4
+        strbt  r1, [r0]
 
 @ Pre-indexed
 @ CHECK: ldr  r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
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