[PATCH] [AArch64] Add register spill code for large super registers such as DPair, DTriple ...

[Jiangning Liu]

Hao,

The patch LGTM now, and could you please add "//FIXME: we should NOT
generate ld/st for register spill/fill" in the test case before upstream?

Thanks,
-Jiangning



2013/12/27 Hao Liu <Hao.Liu at arm.com>

>   Hi Jiangning,
>
>   Thanks for the review.
>   I simplify the code according to your comments. And I find that the
> spill of DPair/DTriple/DQuad registers are always translated into
> QPair/QTriple/QQuad in loadRegFromStackSlot/storeRegToStackSlot according
> to the attached test cases. I think this is caused by the one by one
> correspondence that a D register is always the low 64-bit of a Q register.
> I think there is no need to add load/store of 8B, so I remove the
> LD1x2_8B,LD1x3_8B,LD1x4_8B....ST1x4_8B. If there is such situation to spill
> D register tuples in the future, we can add code according to the code of
> spill Q register tuples.
>
>   Thanks,
>   -Hao
>
> Hi t.p.northover,
>
> http://llvm-reviews.chandlerc.com/D2438
>
> CHANGE SINCE LAST DIFF
>   http://llvm-reviews.chandlerc.com/D2438?vs=6178&id=6279#toc
>
> Files:
>   lib/Target/AArch64/AArch64InstrInfo.cpp
>   lib/Target/AArch64/AArch64RegisterInfo.cpp
>   test/CodeGen/AArch64/neon-vector-list-spill.ll
>



-- 
Thanks,
-Jiangning
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