[llvm] r195026 - R600/SI: Fix illegal VGPR->SGPR copy inside of loop

Tom Stellard thomas.stellard at amd.com
Mon Nov 18 10:50:20 PST 2013


Author: tstellar
Date: Mon Nov 18 12:50:20 2013
New Revision: 195026

URL: http://llvm.org/viewvc/llvm-project?rev=195026&view=rev
Log:
R600/SI: Fix illegal VGPR->SGPR copy inside of loop

Modified:
    llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp
    llvm/trunk/test/CodeGen/R600/sgpr-copy.ll

Modified: llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp?rev=195026&r1=195025&r2=195026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp Mon Nov 18 12:50:20 2013
@@ -188,8 +188,7 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(c
     return false;
 
   SrcRC = inferRegClassFromDef(TRI, MRI, SrcReg, SrcSubReg);
-  return TRI->isSGPRClass(DstRC) &&
-         !TRI->getCommonSubClass(DstRC, SrcRC);
+  return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC);
 }
 
 bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {

Modified: llvm/trunk/test/CodeGen/R600/sgpr-copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/sgpr-copy.ll?rev=195026&r1=195025&r2=195026&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/sgpr-copy.ll (original)
+++ llvm/trunk/test/CodeGen/R600/sgpr-copy.ll Mon Nov 18 12:50:20 2013
@@ -294,3 +294,34 @@ endif:
   store float %6, float addrspace(1)* %out
   ret void
 }
+
+; This test is just checking that we don't crash / assertion fail.
+; CHECK-LABEL: @copy2
+; CHECK: S_ENDPGM
+
+define void @copy2([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
+entry:
+  br label %LOOP68
+
+LOOP68:
+  %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ]
+  %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ]
+  %g = icmp eq i32 0, %t
+  %l = bitcast float %temp4.7 to i32
+  br i1 %g, label %IF70, label %ENDIF69
+
+IF70:
+  %q = icmp ne i32 %l, 13
+  %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
+  ret void
+
+ENDIF69:
+  %u = add i32 %l, %t
+  %v = bitcast i32 %u to float
+  %x = add i32 %t, -1
+  br label %LOOP68
+}
+
+attributes #0 = { "ShaderType"="0" }
+





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