[llvm] r193157 - [mips][msa] Direct Object Emission support for conditional branches.
Matheus Almeida
matheus.almeida at imgtec.com
Tue Oct 22 02:43:33 PDT 2013
Author: matheusalmeida
Date: Tue Oct 22 04:43:32 2013
New Revision: 193157
URL: http://llvm.org/viewvc/llvm-project?rev=193157&view=rev
Log:
[mips][msa] Direct Object Emission support for conditional branches.
These branches have a 16-bit offset (R_MIPS_PC16).
List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v
Added:
llvm/trunk/test/MC/Mips/msa/test_cbranch.s
Modified:
llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td?rev=193157&r1=193156&r2=193157&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td Tue Oct 22 04:43:32 2013
@@ -15,6 +15,10 @@ class MSAInst : MipsInst<(outs), (ins),
let Inst{31-26} = 0b011110;
}
+class MSACBranch : MSAInst {
+ let Inst{31-26} = 0b010001;
+}
+
class PseudoMSA<dag outs, dag ins, list<dag> pattern,
InstrItinClass itin = IIPseudo>:
MipsPseudo<outs, ins, pattern, itin> {
@@ -364,9 +368,23 @@ class MSA_VEC_FMT<bits<5> major, bits<6>
let Inst{5-0} = minor;
}
-class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst {
+class MSA_CBRANCH_FMT<bits<3> major, bits<2> df>: MSACBranch {
+ bits<16> offset;
+ bits<5> wt;
+
+ let Inst{25-23} = major;
+ let Inst{22-21} = df;
+ let Inst{20-16} = wt;
+ let Inst{15-0} = offset;
+}
+
+class MSA_CBRANCH_V_FMT<bits<5> major>: MSACBranch {
+ bits<16> offset;
+ bits<5> wt;
+
let Inst{25-21} = major;
- let Inst{5-0} = minor;
+ let Inst{20-16} = wt;
+ let Inst{15-0} = offset;
}
class SPECIAL_LSA_FMT: MSAInst {
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td?rev=193157&r1=193156&r2=193157&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td Tue Oct 22 04:43:32 2013
@@ -432,12 +432,12 @@ class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101,
class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
-class BNZ_B_ENC : MSA_I10_FMT<0b000, 0b00, 0b001100>;
-class BNZ_H_ENC : MSA_I10_FMT<0b000, 0b01, 0b001100>;
-class BNZ_W_ENC : MSA_I10_FMT<0b000, 0b10, 0b001100>;
-class BNZ_D_ENC : MSA_I10_FMT<0b000, 0b11, 0b001100>;
+class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
+class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
+class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
+class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
-class BNZ_V_ENC : MSA_VEC_FMT<0b01000, 0b011110>;
+class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01000>;
class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
@@ -453,12 +453,12 @@ class BSETI_H_ENC : MSA_BIT_H_FMT<0b100,
class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
-class BZ_B_ENC : MSA_I10_FMT<0b001, 0b00, 0b001100>;
-class BZ_H_ENC : MSA_I10_FMT<0b001, 0b01, 0b001100>;
-class BZ_W_ENC : MSA_I10_FMT<0b001, 0b10, 0b001100>;
-class BZ_D_ENC : MSA_I10_FMT<0b001, 0b11, 0b001100>;
+class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
+class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
+class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
+class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
-class BZ_V_ENC : MSA_VECS10_FMT<0b01001, 0b011110>;
+class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
@@ -1258,10 +1258,10 @@ class MSA_3RF_4RF_DESC_BASE<string instr
InstrItinClass itin = NoItinerary> :
MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
-class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterClass RCWD> {
+class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
dag OutOperandList = (outs);
- dag InOperandList = (ins RCWD:$wd, brtarget:$offset);
- string AsmString = !strconcat(instr_asm, "\t$wd, $offset");
+ dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
+ string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
list<dag> Pattern = [];
InstrItinClass Itinerary = IIBranch;
bit isBranch = 1;
@@ -1511,12 +1511,12 @@ class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE
class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", int_mips_bnegi_d,
MSA128DOpnd>;
-class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128B>;
-class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128H>;
-class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128W>;
-class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128D>;
+class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
+class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
+class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
+class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
-class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128B>;
+class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
class BSEL_V_DESC {
dag OutOperandList = (outs MSA128BOpnd:$wd);
@@ -1556,12 +1556,12 @@ class BSETI_W_DESC : MSA_BIT_W_DESC_BASE
class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", int_mips_bseti_d,
MSA128DOpnd>;
-class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128B>;
-class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128H>;
-class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128W>;
-class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128D>;
+class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
+class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
+class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
+class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
-class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128B>;
+class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
IsCommutable;
Added: llvm/trunk/test/MC/Mips/msa/test_cbranch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/msa/test_cbranch.s?rev=193157&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/msa/test_cbranch.s (added)
+++ llvm/trunk/test/MC/Mips/msa/test_cbranch.s Tue Oct 22 04:43:32 2013
@@ -0,0 +1,78 @@
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s
+#
+#CHECK: bnz.b $w0, 4 # encoding: [0x47,0x80,0x00,0x01]
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bnz.h $w1, 16 # encoding: [0x47,0xa1,0x00,0x04]
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bnz.w $w2, 128 # encoding: [0x47,0xc2,0x00,0x20]
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bnz.d $w3, -128 # encoding: [0x47,0xe3,0xff,0xe0]
+#CHECK: bnz.b $w0, SYMBOL0 # encoding: [0x47'A',0x80'A',0x00,0x00]
+ # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bnz.h $w1, SYMBOL1 # encoding: [0x47'A',0xa1'A',0x00,0x00]
+ # fixup A - offset: 0, value: SYMBOL1, kind: fixup_Mips_PC16
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bnz.w $w2, SYMBOL2 # encoding: [0x47'A',0xc2'A',0x00,0x00]
+ # fixup A - offset: 0, value: SYMBOL2, kind: fixup_Mips_PC16
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bnz.d $w3, SYMBOL3 # encoding: [0x47'A',0xe3'A',0x00,0x00]
+ # fixup A - offset: 0, value: SYMBOL3, kind: fixup_Mips_PC16
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+
+#CHECK: bnz.v $w0, 4 # encoding: [0x45,0x00,0x00,0x01]
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bnz.v $w0, SYMBOL0 # encoding: [0x45'A',A,0x00,0x00]
+ # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+
+#CHECK: bz.b $w0, 128 # encoding: [0x47,0x00,0x00,0x20]
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bz.h $w1, 256 # encoding: [0x47,0x21,0x00,0x40]
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bz.w $w2, 512 # encoding: [0x47,0x42,0x00,0x80]
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bz.d $w3, -1024 # encoding: [0x47,0x63,0xff,0x00]
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bz.b $w0, SYMBOL0 # encoding: [0x47'A',A,0x00,0x00]
+ # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bz.h $w1, SYMBOL1 # encoding: [0x47'A',0x21'A',0x00,0x00]
+ # fixup A - offset: 0, value: SYMBOL1, kind: fixup_Mips_PC16
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bz.w $w2, SYMBOL2 # encoding: [0x47'A',0x42'A',0x00,0x00]
+ # fixup A - offset: 0, value: SYMBOL2, kind: fixup_Mips_PC16
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bz.d $w3, SYMBOL3 # encoding: [0x47'A',0x63'A',0x00,0x00]
+ # fixup A - offset: 0, value: SYMBOL3, kind: fixup_Mips_PC16
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+
+#CHECK: bz.v $w0, 4 # encoding: [0x45,0x60,0x00,0x01]
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+#CHECK: bz.v $w0, SYMBOL0 # encoding: [0x45'A',0x60'A',0x00,0x00]
+ # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16
+#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+
+bnz.b $w0, 4
+bnz.h $w1, 16
+bnz.w $w2, 128
+bnz.d $w3, -128
+bnz.b $w0, SYMBOL0
+bnz.h $w1, SYMBOL1
+bnz.w $w2, SYMBOL2
+bnz.d $w3, SYMBOL3
+
+bnz.v $w0, 4
+bnz.v $w0, SYMBOL0
+
+bz.b $w0, 128
+bz.h $w1, 256
+bz.w $w2, 512
+bz.d $w3, -1024
+bz.b $w0, SYMBOL0
+bz.h $w1, SYMBOL1
+bz.w $w2, SYMBOL2
+bz.d $w3, SYMBOL3
+
+bz.v $w0, 4
+bz.v $w0, SYMBOL0
More information about the llvm-commits
mailing list