[llvm] r191774 - [SystemZ] Add immediate addition involving high words
Richard Sandiford
rsandifo at linux.vnet.ibm.com
Tue Oct 1 07:53:46 PDT 2013
Author: rsandifo
Date: Tue Oct 1 09:53:46 2013
New Revision: 191774
URL: http://llvm.org/viewvc/llvm-project?rev=191774&view=rev
Log:
[SystemZ] Add immediate addition involving high words
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/test/CodeGen/SystemZ/asm-18.ll
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good-z196.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=191774&r1=191773&r2=191774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Tue Oct 1 09:53:46 2013
@@ -1386,6 +1386,25 @@ class BinaryRIPseudo<SDPatternOperator o
let Constraints = "$R1 = $R1src";
}
+// Like BinaryRIE, but expanded after RA depending on the choice of register.
+class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
+ Immediate imm>
+ : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
+ [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
+
+// Like BinaryRIAndK, but expanded after RA depending on the choice of register.
+multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
+ RegisterOperand cls, Immediate imm> {
+ let NumOpsKey = key in {
+ let NumOpsValue = "3" in
+ def K : BinaryRIEPseudo<null_frag, cls, imm>,
+ Requires<[FeatureHighWord, FeatureDistinctOps]>;
+ let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
+ def "" : BinaryRIPseudo<operator, cls, imm>,
+ Requires<[FeatureHighWord]>;
+ }
+}
+
// Like CompareRI, but expanded after RA depending on the choice of register.
class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
Immediate imm>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=191774&r1=191773&r2=191774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Tue Oct 1 09:53:46 2013
@@ -107,6 +107,28 @@ void SystemZInstrInfo::expandRIPseudo(Ma
MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm()));
}
+// MI is a three-operand RIE-style pseudo instruction. Replace it with
+// LowOpcode3 if the registers are both low GR32s, otherwise use a move
+// followed by HighOpcode or LowOpcode, depending on whether the target
+// is a high or low GR32.
+void SystemZInstrInfo::expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
+ unsigned LowOpcodeK,
+ unsigned HighOpcode) const {
+ unsigned DestReg = MI->getOperand(0).getReg();
+ unsigned SrcReg = MI->getOperand(1).getReg();
+ bool DestIsHigh = isHighReg(DestReg);
+ bool SrcIsHigh = isHighReg(SrcReg);
+ if (!DestIsHigh && !SrcIsHigh)
+ MI->setDesc(get(LowOpcodeK));
+ else {
+ emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
+ DestReg, SrcReg, SystemZ::LR, 32,
+ MI->getOperand(1).isKill());
+ MI->setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
+ MI->getOperand(1).setReg(DestReg);
+ }
+}
+
// MI is an RXY-style pseudo instruction. Replace it with LowOpcode
// if the first operand is a low GR32 and HighOpcode if the first operand
// is a high GR32.
@@ -651,6 +673,7 @@ SystemZInstrInfo::convertToThreeAddress(
LiveVariables *LV) const {
MachineInstr *MI = MBBI;
MachineBasicBlock *MBB = MI->getParent();
+ MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
unsigned Opcode = MI->getOpcode();
unsigned NumOps = MI->getNumOperands();
@@ -660,10 +683,23 @@ SystemZInstrInfo::convertToThreeAddress(
// because it tends to be shorter and because some instructions
// have memory forms that can be used during spilling.
if (TM.getSubtargetImpl()->hasDistinctOps()) {
+ MachineOperand &Dest = MI->getOperand(0);
+ MachineOperand &Src = MI->getOperand(1);
+ unsigned DestReg = Dest.getReg();
+ unsigned SrcReg = Src.getReg();
+ // AHIMux is only really a three-operand instruction when both operands
+ // are low registers. Try to constrain both operands to be low if
+ // possible.
+ if (Opcode == SystemZ::AHIMux &&
+ TargetRegisterInfo::isVirtualRegister(DestReg) &&
+ TargetRegisterInfo::isVirtualRegister(SrcReg) &&
+ MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
+ MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
+ MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
+ MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
+ }
int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
if (ThreeOperandOpcode >= 0) {
- MachineOperand &Dest = MI->getOperand(0);
- MachineOperand &Src = MI->getOperand(1);
MachineInstrBuilder MIB =
BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode))
.addOperand(Dest);
@@ -918,6 +954,18 @@ SystemZInstrInfo::expandPostRAPseudo(Mac
expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
return true;
+ case SystemZ::AHIMux:
+ expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
+ return true;
+
+ case SystemZ::AHIMuxK:
+ expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
+ return true;
+
+ case SystemZ::AFIMux:
+ expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
+ return true;
+
case SystemZ::RISBMux: {
bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h?rev=191774&r1=191773&r2=191774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h Tue Oct 1 09:53:46 2013
@@ -118,6 +118,8 @@ class SystemZInstrInfo : public SystemZG
void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
void expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
unsigned HighOpcode, bool ConvertHigh) const;
+ void expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
+ unsigned LowOpcodeK, unsigned HighOpcode) const;
void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
unsigned HighOpcode) const;
void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=191774&r1=191773&r2=191774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Tue Oct 1 09:53:46 2013
@@ -685,11 +685,16 @@ let Defs = [CC], CCValues = 0xF, Compare
def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
// Addition of signed 16-bit immediates.
+ defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>;
defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>;
defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
// Addition of signed 32-bit immediates.
+ def AFIMux : BinaryRIPseudo<add, GRX32, simm32>,
+ Requires<[FeatureHighWord]>;
def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
+ def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>,
+ Requires<[FeatureHighWord]>;
def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
// Addition of memory.
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-18.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-18.ll?rev=191774&r1=191773&r2=191774&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-18.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-18.ll Tue Oct 1 09:53:46 2013
@@ -554,3 +554,118 @@ define i32 @f25(i32 %old) {
"=r,h,h"(i32 %sel3, i32 %sel4)
ret i32 %res2
}
+
+; Test two-operand halfword immediate addition involving high registers.
+define void @f26() {
+; CHECK-LABEL: f26:
+; CHECK: stepa [[REG:%r[0-5]]]
+; CHECK: aih [[REG]], -32768
+; CHECK: stepb [[REG]]
+; CHECK: aih [[REG]], 1
+; CHECK: stepc [[REG]]
+; CHECK: aih [[REG]], 32767
+; CHECK: stepd [[REG]]
+; CHECK: br %r14
+ %res1 = call i32 asm "stepa $0", "=h"()
+ %add1 = add i32 %res1, -32768
+ %res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %add1)
+ %add2 = add i32 %res2, 1
+ %res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %add2)
+ %add3 = add i32 %res3, 32767
+ call void asm sideeffect "stepd $0", "h"(i32 %add3)
+ ret void
+}
+
+; Test two-operand halfword immediate addition involving low registers.
+define void @f27() {
+; CHECK-LABEL: f27:
+; CHECK: stepa [[REG:%r[0-5]]]
+; CHECK: ahi [[REG]], -32768
+; CHECK: stepb [[REG]]
+; CHECK: ahi [[REG]], 1
+; CHECK: stepc [[REG]]
+; CHECK: ahi [[REG]], 32767
+; CHECK: stepd [[REG]]
+; CHECK: br %r14
+ %res1 = call i32 asm "stepa $0", "=r"()
+ %add1 = add i32 %res1, -32768
+ %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %add1)
+ %add2 = add i32 %res2, 1
+ %res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %add2)
+ %add3 = add i32 %res3, 32767
+ call void asm sideeffect "stepd $0", "r"(i32 %add3)
+ ret void
+}
+
+; Test three-operand halfword immediate addition involving mixtures of low
+; and high registers. RISBHG/AIH would be OK too, instead of AHIK/RISBHG.
+define i32 @f28(i32 %old) {
+; CHECK-LABEL: f28:
+; CHECK: ahik [[REG1:%r[0-5]]], %r2, 14
+; CHECK: stepa %r2, [[REG1]]
+; CHECK: ahik [[TMP:%r[0-5]]], [[REG1]], 254
+; CHECK: risbhg [[REG2:%r[0-5]]], [[TMP]], 0, 159, 32
+; CHECK: stepb [[REG1]], [[REG2]]
+; CHECK: risbhg [[REG3:%r[0-5]]], [[REG2]], 0, 159, 0
+; CHECK: aih [[REG3]], 127
+; CHECK: stepc [[REG2]], [[REG3]]
+; CHECK: risblg %r2, [[REG3]], 0, 159, 32
+; CHECK: ahi %r2, 128
+; CHECK: stepd [[REG3]], %r2
+; CHECK: br %r14
+ %add1 = add i32 %old, 14
+ %res1 = call i32 asm "stepa $1, $2",
+ "=r,r,0"(i32 %old, i32 %add1)
+ %add2 = add i32 %res1, 254
+ %res2 = call i32 asm "stepb $1, $2",
+ "=h,r,0"(i32 %res1, i32 %add2)
+ %add3 = add i32 %res2, 127
+ %res3 = call i32 asm "stepc $1, $2",
+ "=h,h,0"(i32 %res2, i32 %add3)
+ %add4 = add i32 %res3, 128
+ %res4 = call i32 asm "stepd $1, $2",
+ "=r,h,0"(i32 %res3, i32 %add4)
+ ret i32 %res4
+}
+
+; Test large immediate addition involving high registers.
+define void @f29() {
+; CHECK-LABEL: f29:
+; CHECK: stepa [[REG:%r[0-5]]]
+; CHECK: aih [[REG]], -32769
+; CHECK: stepb [[REG]]
+; CHECK: aih [[REG]], 32768
+; CHECK: stepc [[REG]]
+; CHECK: aih [[REG]], 1000000000
+; CHECK: stepd [[REG]]
+; CHECK: br %r14
+ %res1 = call i32 asm "stepa $0", "=h"()
+ %add1 = add i32 %res1, -32769
+ %res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %add1)
+ %add2 = add i32 %res2, 32768
+ %res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %add2)
+ %add3 = add i32 %res3, 1000000000
+ call void asm sideeffect "stepd $0", "h"(i32 %add3)
+ ret void
+}
+
+; Test large immediate addition involving low registers.
+define void @f30() {
+; CHECK-LABEL: f30:
+; CHECK: stepa [[REG:%r[0-5]]]
+; CHECK: afi [[REG]], -32769
+; CHECK: stepb [[REG]]
+; CHECK: afi [[REG]], 32768
+; CHECK: stepc [[REG]]
+; CHECK: afi [[REG]], 1000000000
+; CHECK: stepd [[REG]]
+; CHECK: br %r14
+ %res1 = call i32 asm "stepa $0", "=r"()
+ %add1 = add i32 %res1, -32769
+ %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %add1)
+ %add2 = add i32 %res2, 32768
+ %res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %add2)
+ %add3 = add i32 %res3, 1000000000
+ call void asm sideeffect "stepd $0", "r"(i32 %add3)
+ ret void
+}
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=191774&r1=191773&r2=191774&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Tue Oct 1 09:53:46 2013
@@ -349,6 +349,24 @@
# CHECK: ahy %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x7a
+# CHECK: aih %r0, -2147483648
+0xcc 0x08 0x80 0x00 0x00 0x00
+
+# CHECK: aih %r0, -1
+0xcc 0x08 0xff 0xff 0xff 0xff
+
+# CHECK: aih %r0, 0
+0xcc 0x08 0x00 0x00 0x00 0x00
+
+# CHECK: aih %r0, 1
+0xcc 0x08 0x00 0x00 0x00 0x01
+
+# CHECK: aih %r0, 2147483647
+0xcc 0x08 0x7f 0xff 0xff 0xff
+
+# CHECK: aih %r15, 0
+0xcc 0xf8 0x00 0x00 0x00 0x00
+
# CHECK: alcgr %r0, %r0
0xb9 0x88 0x00 0x00
Modified: llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-z196.s?rev=191774&r1=191773&r2=191774&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-z196.s Tue Oct 1 09:53:46 2013
@@ -25,6 +25,14 @@
ahik %r0, %r1, foo
#CHECK: error: invalid operand
+#CHECK: aih %r0, (-1 << 31) - 1
+#CHECK: error: invalid operand
+#CHECK: aih %r0, (1 << 31)
+
+ aih %r0, (-1 << 31) - 1
+ aih %r0, (1 << 31)
+
+#CHECK: error: invalid operand
#CHECK: fidbra %f0, 0, %f0, -1
#CHECK: error: invalid operand
#CHECK: fidbra %f0, 0, %f0, 16
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=191774&r1=191773&r2=191774&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Tue Oct 1 09:53:46 2013
@@ -128,6 +128,11 @@
ahy %r0, -524289
ahy %r0, 524288
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: aih %r0, 0
+
+ aih %r0, 0
+
#CHECK: error: invalid operand
#CHECK: al %r0, -1
#CHECK: error: invalid operand
Modified: llvm/trunk/test/MC/SystemZ/insn-good-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-z196.s?rev=191774&r1=191773&r2=191774&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-z196.s Tue Oct 1 09:53:46 2013
@@ -49,6 +49,20 @@
ahik %r15, %r0, 0
ahik %r7, %r8, -16
+#CHECK: aih %r0, -2147483648 # encoding: [0xcc,0x08,0x80,0x00,0x00,0x00]
+#CHECK: aih %r0, -1 # encoding: [0xcc,0x08,0xff,0xff,0xff,0xff]
+#CHECK: aih %r0, 0 # encoding: [0xcc,0x08,0x00,0x00,0x00,0x00]
+#CHECK: aih %r0, 1 # encoding: [0xcc,0x08,0x00,0x00,0x00,0x01]
+#CHECK: aih %r0, 2147483647 # encoding: [0xcc,0x08,0x7f,0xff,0xff,0xff]
+#CHECK: aih %r15, 0 # encoding: [0xcc,0xf8,0x00,0x00,0x00,0x00]
+
+ aih %r0, -1 << 31
+ aih %r0, -1
+ aih %r0, 0
+ aih %r0, 1
+ aih %r0, (1 << 31) - 1
+ aih %r15, 0
+
#CHECK: alghsik %r0, %r0, -32768 # encoding: [0xec,0x00,0x80,0x00,0x00,0xdb]
#CHECK: alghsik %r0, %r0, -1 # encoding: [0xec,0x00,0xff,0xff,0x00,0xdb]
#CHECK: alghsik %r0, %r0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0xdb]
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