[llvm] r191773 - [SystemZ] Extend test-under-mask support to high GR32s
Richard Sandiford
rsandifo at linux.vnet.ibm.com
Tue Oct 1 07:41:52 PDT 2013
Author: rsandifo
Date: Tue Oct 1 09:41:52 2013
New Revision: 191773
URL: http://llvm.org/viewvc/llvm-project?rev=191773&view=rev
Log:
[SystemZ] Extend test-under-mask support to high GR32s
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZPatterns.td
llvm/trunk/test/CodeGen/SystemZ/asm-18.ll
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=191773&r1=191772&r2=191773&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Tue Oct 1 09:41:52 2013
@@ -1386,6 +1386,11 @@ class BinaryRIPseudo<SDPatternOperator o
let Constraints = "$R1 = $R1src";
}
+// Like CompareRI, but expanded after RA depending on the choice of register.
+class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
+ Immediate imm>
+ : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
+
// Like StoreRXY, but expanded after RA depending on the choice of registers.
class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
bits<5> bytes, AddressingMode mode = bdxaddr20only>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=191773&r1=191772&r2=191773&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Tue Oct 1 09:41:52 2013
@@ -910,6 +910,14 @@ SystemZInstrInfo::expandPostRAPseudo(Mac
expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
return true;
+ case SystemZ::TMLMux:
+ expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
+ return true;
+
+ case SystemZ::TMHMux:
+ expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
+ return true;
+
case SystemZ::RISBMux: {
bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=191773&r1=191772&r2=191773&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Tue Oct 1 09:41:52 2013
@@ -1140,16 +1140,22 @@ let mayLoad = 1, Defs = [CC], Uses = [R0
// Test under mask.
let Defs = [CC] in {
+ // TMxMux expands to TM[LH]x, depending on the choice of register.
+ def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>,
+ Requires<[FeatureHighWord]>;
+ def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>,
+ Requires<[FeatureHighWord]>;
def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
-
- def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GR64, imm64hl16>;
- def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GR64, imm64hh16>;
+ def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>;
+ def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>;
defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
}
-def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16>;
-def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16>;
+def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16, subreg_l32>;
+def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16, subreg_l32>;
+def : CompareGR64RI<TMHL, z_tm_reg, imm64hl16, subreg_h32>;
+def : CompareGR64RI<TMHH, z_tm_reg, imm64hh16, subreg_h32>;
//===----------------------------------------------------------------------===//
// Prefetch
Modified: llvm/trunk/lib/Target/SystemZ/SystemZPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZPatterns.td?rev=191773&r1=191772&r2=191773&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZPatterns.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZPatterns.td Tue Oct 1 09:41:52 2013
@@ -113,11 +113,11 @@ multiclass CondStores64<Instruction insn
}
// INSN performs a comparison between a 32-bit register and a constant.
-// Record that it is equivalent to comparing the low word of a GR64 with IMM.
+// Record that it is equivalent to comparing subreg SUBREG of a GR64 with IMM.
class CompareGR64RI<Instruction insn, SDPatternOperator compare,
- Immediate imm>
+ Immediate imm, SubRegIndex subreg>
: Pat<(compare GR64:$R1, imm:$I2),
- (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32),
+ (insn (EXTRACT_SUBREG GR64:$R1, subreg),
(imm.OperandTransform imm:$I2))>;
// Try to use MVC instruction INSN for a load of type LOAD followed by a store
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-18.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-18.ll?rev=191773&r1=191772&r2=191773&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-18.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-18.ll Tue Oct 1 09:41:52 2013
@@ -525,3 +525,32 @@ define i32 @f24(i32 %old) {
"=r,h,h,0"(i32 %res1, i32 %and3, i32 %and4)
ret i32 %res2
}
+
+; Test TMxx involving mixtures of high and low registers.
+define i32 @f25(i32 %old) {
+; CHECK-LABEL: f25:
+; CHECK-DAG: tmll %r2, 1
+; CHECK-DAG: tmlh %r2, 1
+; CHECK: stepa [[REG1:%r[0-5]]],
+; CHECK-DAG: tmhl [[REG1]], 1
+; CHECK-DAG: tmhh [[REG1]], 1
+; CHECK: stepb %r2,
+; CHECK: br %r14
+ %and1 = and i32 %old, 1
+ %and2 = and i32 %old, 65536
+ %cmp1 = icmp eq i32 %and1, 0
+ %cmp2 = icmp eq i32 %and2, 0
+ %sel1 = select i1 %cmp1, i32 100, i32 200
+ %sel2 = select i1 %cmp2, i32 100, i32 200
+ %res1 = call i32 asm "stepa $0, $1, $2",
+ "=h,r,r"(i32 %sel1, i32 %sel2)
+ %and3 = and i32 %res1, 1
+ %and4 = and i32 %res1, 65536
+ %cmp3 = icmp eq i32 %and3, 0
+ %cmp4 = icmp eq i32 %and4, 0
+ %sel3 = select i1 %cmp3, i32 100, i32 200
+ %sel4 = select i1 %cmp4, i32 100, i32 200
+ %res2 = call i32 asm "stepb $0, $1, $2",
+ "=r,h,h"(i32 %sel3, i32 %sel4)
+ ret i32 %res2
+}
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