[llvm] r191743 - [SystemZ] Add truncating high-word stores (STCH and STHH)
Richard Sandiford
rsandifo at linux.vnet.ibm.com
Tue Oct 1 05:22:50 PDT 2013
Author: rsandifo
Date: Tue Oct 1 07:22:49 2013
New Revision: 191743
URL: http://llvm.org/viewvc/llvm-project?rev=191743&view=rev
Log:
[SystemZ] Add truncating high-word stores (STCH and STHH)
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/test/CodeGen/SystemZ/asm-18.ll
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good-z196.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=191743&r1=191742&r2=191743&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Tue Oct 1 07:22:49 2013
@@ -826,6 +826,14 @@ SystemZInstrInfo::expandPostRAPseudo(Mac
expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
return true;
+ case SystemZ::STCMux:
+ expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
+ return true;
+
+ case SystemZ::STHMux:
+ expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
+ return true;
+
case SystemZ::STMux:
expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
return true;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=191743&r1=191742&r2=191743&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Tue Oct 1 07:22:49 2013
@@ -488,10 +488,22 @@ def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E,
def : Pat<(i32 (trunc GR64:$src)),
(EXTRACT_SUBREG GR64:$src, subreg_l32)>;
-// Truncations of 32-bit registers to memory.
-defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
-defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
-def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
+// Truncations of 32-bit registers to 8-bit memory. STCMux expands to
+// STC, STCY or STCH, depending on the choice of register.
+def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,
+ Requires<[FeatureHighWord]>;
+defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
+def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,
+ Requires<[FeatureHighWord]>;
+
+// Truncations of 32-bit registers to 16-bit memory. STHMux expands to
+// STH, STHY or STHH, depending on the choice of register.
+def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,
+ Requires<[FeatureHighWord]>;
+defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
+def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,
+ Requires<[FeatureHighWord]>;
+def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
// Truncations of 64-bit registers to memory.
defm : StoreGR64Pair<STC, STCY, truncstorei8>;
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-18.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-18.ll?rev=191743&r1=191742&r2=191743&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-18.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-18.ll Tue Oct 1 07:22:49 2013
@@ -146,3 +146,49 @@ define void @f6(i16 *%ptr1, i16 *%ptr2)
"h,r,h,r"(i32 %ext1, i32 %ext2, i32 %ext3, i32 %ext4)
ret void
}
+
+; Test truncating stores of high and low registers into 8-bit memory.
+define void @f7(i8 *%ptr1, i8 *%ptr2) {
+; CHECK-LABEL: f7:
+; CHECK: blah [[REG1:%r[0-5]]], [[REG2:%r[0-5]]]
+; CHECK-DAG: stch [[REG1]], 0(%r2)
+; CHECK-DAG: stc [[REG2]], 0(%r3)
+; CHECK-DAG: stch [[REG1]], 4096(%r2)
+; CHECK-DAG: stcy [[REG2]], 524287(%r3)
+; CHECK: br %r14
+ %res = call { i32, i32 } asm "blah $0, $1", "=h,=r"()
+ %res1 = extractvalue { i32, i32 } %res, 0
+ %res2 = extractvalue { i32, i32 } %res, 1
+ %trunc1 = trunc i32 %res1 to i8
+ %trunc2 = trunc i32 %res2 to i8
+ %ptr3 = getelementptr i8 *%ptr1, i64 4096
+ %ptr4 = getelementptr i8 *%ptr2, i64 524287
+ store i8 %trunc1, i8 *%ptr1
+ store i8 %trunc2, i8 *%ptr2
+ store i8 %trunc1, i8 *%ptr3
+ store i8 %trunc2, i8 *%ptr4
+ ret void
+}
+
+; Test truncating stores of high and low registers into 16-bit memory.
+define void @f8(i16 *%ptr1, i16 *%ptr2) {
+; CHECK-LABEL: f8:
+; CHECK: blah [[REG1:%r[0-5]]], [[REG2:%r[0-5]]]
+; CHECK-DAG: sthh [[REG1]], 0(%r2)
+; CHECK-DAG: sth [[REG2]], 0(%r3)
+; CHECK-DAG: sthh [[REG1]], 4096(%r2)
+; CHECK-DAG: sthy [[REG2]], 524286(%r3)
+; CHECK: br %r14
+ %res = call { i32, i32 } asm "blah $0, $1", "=h,=r"()
+ %res1 = extractvalue { i32, i32 } %res, 0
+ %res2 = extractvalue { i32, i32 } %res, 1
+ %trunc1 = trunc i32 %res1 to i16
+ %trunc2 = trunc i32 %res2 to i16
+ %ptr3 = getelementptr i16 *%ptr1, i64 2048
+ %ptr4 = getelementptr i16 *%ptr2, i64 262143
+ store i16 %trunc1, i16 *%ptr1
+ store i16 %trunc2, i16 *%ptr2
+ store i16 %trunc1, i16 *%ptr3
+ store i16 %trunc2, i16 *%ptr4
+ ret void
+}
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=191743&r1=191742&r2=191743&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Tue Oct 1 07:22:49 2013
@@ -6664,6 +6664,36 @@
# CHECK: stc %r15, 0
0x42 0xf0 0x00 0x00
+# CHECK: stch %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0xc3
+
+# CHECK: stch %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0xc3
+
+# CHECK: stch %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0xc3
+
+# CHECK: stch %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0xc3
+
+# CHECK: stch %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0xc3
+
+# CHECK: stch %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0xc3
+
+# CHECK: stch %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0xc3
+
+# CHECK: stch %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0xc3
+
+# CHECK: stch %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0xc3
+
+# CHECK: stch %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0xc3
+
# CHECK: stcy %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x72
@@ -6847,6 +6877,36 @@
# CHECK: sth %r15, 0
0x40 0xf0 0x00 0x00
+# CHECK: sthh %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0xc7
+
+# CHECK: sthh %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0xc7
+
+# CHECK: sthh %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0xc7
+
+# CHECK: sthh %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0xc7
+
+# CHECK: sthh %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0xc7
+
+# CHECK: sthh %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0xc7
+
+# CHECK: sthh %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0xc7
+
+# CHECK: sthh %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0xc7
+
+# CHECK: sthh %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0xc7
+
+# CHECK: sthh %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0xc7
+
# CHECK: stfh %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0xcb
Modified: llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-z196.s?rev=191743&r1=191742&r2=191743&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-z196.s Tue Oct 1 07:22:49 2013
@@ -245,6 +245,22 @@
srlk %r0,%r0,0(%r1,%r2)
#CHECK: error: invalid operand
+#CHECK: stch %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: stch %r0, 524288
+
+ stch %r0, -524289
+ stch %r0, 524288
+
+#CHECK: error: invalid operand
+#CHECK: sthh %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: sthh %r0, 524288
+
+ sthh %r0, -524289
+ sthh %r0, 524288
+
+#CHECK: error: invalid operand
#CHECK: stfh %r0, -524289
#CHECK: error: invalid operand
#CHECK: stfh %r0, 524288
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=191743&r1=191742&r2=191743&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Tue Oct 1 07:22:49 2013
@@ -2915,6 +2915,11 @@
stc %r0, -1
stc %r0, 4096
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: stch %r0, 0
+
+ stch %r0, 0
+
#CHECK: error: invalid operand
#CHECK: stcy %r0, -524289
#CHECK: error: invalid operand
@@ -2985,6 +2990,11 @@
sth %r0, -1
sth %r0, 4096
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: sthh %r0, 0
+
+ sthh %r0, 0
+
#CHECK: error: offset out of range
#CHECK: sthrl %r0, -0x1000000002
#CHECK: error: offset out of range
Modified: llvm/trunk/test/MC/SystemZ/insn-good-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-z196.s?rev=191743&r1=191742&r2=191743&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-z196.s Tue Oct 1 07:22:49 2013
@@ -647,6 +647,50 @@
srlk %r0,%r0,524287(%r1)
srlk %r0,%r0,524287(%r15)
+#CHECK: stch %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xc3]
+#CHECK: stch %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xc3]
+#CHECK: stch %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xc3]
+#CHECK: stch %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0xc3]
+#CHECK: stch %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0xc3]
+#CHECK: stch %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0xc3]
+#CHECK: stch %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0xc3]
+#CHECK: stch %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0xc3]
+#CHECK: stch %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0xc3]
+#CHECK: stch %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0xc3]
+
+ stch %r0, -524288
+ stch %r0, -1
+ stch %r0, 0
+ stch %r0, 1
+ stch %r0, 524287
+ stch %r0, 0(%r1)
+ stch %r0, 0(%r15)
+ stch %r0, 524287(%r1,%r15)
+ stch %r0, 524287(%r15,%r1)
+ stch %r15, 0
+
+#CHECK: sthh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xc7]
+#CHECK: sthh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xc7]
+#CHECK: sthh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xc7]
+#CHECK: sthh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0xc7]
+#CHECK: sthh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0xc7]
+#CHECK: sthh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0xc7]
+#CHECK: sthh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0xc7]
+#CHECK: sthh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0xc7]
+#CHECK: sthh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0xc7]
+#CHECK: sthh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0xc7]
+
+ sthh %r0, -524288
+ sthh %r0, -1
+ sthh %r0, 0
+ sthh %r0, 1
+ sthh %r0, 524287
+ sthh %r0, 0(%r1)
+ sthh %r0, 0(%r15)
+ sthh %r0, 524287(%r1,%r15)
+ sthh %r0, 524287(%r15,%r1)
+ sthh %r15, 0
+
#CHECK: stfh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xcb]
#CHECK: stfh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xcb]
#CHECK: stfh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xcb]
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