[llvm] r191742 - [SystemZ] Add zero-extending high-word loads (LLCH and LLHH)
Richard Sandiford
rsandifo at linux.vnet.ibm.com
Tue Oct 1 05:19:09 PDT 2013
Author: rsandifo
Date: Tue Oct 1 07:19:08 2013
New Revision: 191742
URL: http://llvm.org/viewvc/llvm-project?rev=191742&view=rev
Log:
[SystemZ] Add zero-extending high-word loads (LLCH and LLHH)
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/test/CodeGen/SystemZ/asm-18.ll
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good-z196.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=191742&r1=191741&r2=191742&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Tue Oct 1 07:19:08 2013
@@ -814,6 +814,14 @@ SystemZInstrInfo::expandPostRAPseudo(Mac
expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
return true;
+ case SystemZ::LLCMux:
+ expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
+ return true;
+
+ case SystemZ::LLHMux:
+ expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
+ return true;
+
case SystemZ::LMux:
expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
return true;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=191742&r1=191741&r2=191742&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Tue Oct 1 07:19:08 2013
@@ -456,9 +456,21 @@ let neverHasSideEffects = 1 in {
def : Pat<(and GR64:$src, 0xffffffff),
(LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
-// 32-bit extensions from memory.
-def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
+// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH,
+// depending on the choice of register.
+def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>,
+ Requires<[FeatureHighWord]>;
+def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
+def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GR32, 1>,
+ Requires<[FeatureHighWord]>;
+
+// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH,
+// depending on the choice of register.
+def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>,
+ Requires<[FeatureHighWord]>;
def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
+def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GR32, 2>,
+ Requires<[FeatureHighWord]>;
def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
// 64-bit extensions from memory.
Modified: llvm/trunk/test/CodeGen/SystemZ/asm-18.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/asm-18.ll?rev=191742&r1=191741&r2=191742&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/asm-18.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/asm-18.ll Tue Oct 1 07:19:08 2013
@@ -98,3 +98,51 @@ define void @f4(i16 *%ptr1, i16 *%ptr2)
"h,r,h,r"(i32 %ext1, i32 %ext2, i32 %ext3, i32 %ext4)
ret void
}
+
+; Test zero-extending 8-bit loads into mixtures of high and low registers.
+define void @f5(i8 *%ptr1, i8 *%ptr2) {
+; CHECK-LABEL: f5:
+; CHECK-DAG: llch [[REG1:%r[0-5]]], 0(%r2)
+; CHECK-DAG: llc [[REG2:%r[0-5]]], 0(%r3)
+; CHECK-DAG: llch [[REG3:%r[0-5]]], 4096(%r2)
+; CHECK-DAG: llc [[REG4:%r[0-5]]], 524287(%r3)
+; CHECK: blah [[REG1]], [[REG2]]
+; CHECK: br %r14
+ %ptr3 = getelementptr i8 *%ptr1, i64 4096
+ %ptr4 = getelementptr i8 *%ptr2, i64 524287
+ %val1 = load i8 *%ptr1
+ %val2 = load i8 *%ptr2
+ %val3 = load i8 *%ptr3
+ %val4 = load i8 *%ptr4
+ %ext1 = zext i8 %val1 to i32
+ %ext2 = zext i8 %val2 to i32
+ %ext3 = zext i8 %val3 to i32
+ %ext4 = zext i8 %val4 to i32
+ call void asm sideeffect "blah $0, $1, $2, $3",
+ "h,r,h,r"(i32 %ext1, i32 %ext2, i32 %ext3, i32 %ext4)
+ ret void
+}
+
+; Test zero-extending 16-bit loads into mixtures of high and low registers.
+define void @f6(i16 *%ptr1, i16 *%ptr2) {
+; CHECK-LABEL: f6:
+; CHECK-DAG: llhh [[REG1:%r[0-5]]], 0(%r2)
+; CHECK-DAG: llh [[REG2:%r[0-5]]], 0(%r3)
+; CHECK-DAG: llhh [[REG3:%r[0-5]]], 4096(%r2)
+; CHECK-DAG: llh [[REG4:%r[0-5]]], 524286(%r3)
+; CHECK: blah [[REG1]], [[REG2]]
+; CHECK: br %r14
+ %ptr3 = getelementptr i16 *%ptr1, i64 2048
+ %ptr4 = getelementptr i16 *%ptr2, i64 262143
+ %val1 = load i16 *%ptr1
+ %val2 = load i16 *%ptr2
+ %val3 = load i16 *%ptr3
+ %val4 = load i16 *%ptr4
+ %ext1 = zext i16 %val1 to i32
+ %ext2 = zext i16 %val2 to i32
+ %ext3 = zext i16 %val3 to i32
+ %ext4 = zext i16 %val4 to i32
+ call void asm sideeffect "blah $0, $1, $2, $3",
+ "h,r,h,r"(i32 %ext1, i32 %ext2, i32 %ext3, i32 %ext4)
+ ret void
+}
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=191742&r1=191741&r2=191742&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Tue Oct 1 07:19:08 2013
@@ -3166,6 +3166,36 @@
# CHECK: llc %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x94
+# CHECK: llch %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0xc2
+
+# CHECK: llch %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0xc2
+
+# CHECK: llch %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0xc2
+
+# CHECK: llch %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0xc2
+
+# CHECK: llch %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0xc2
+
+# CHECK: llch %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0xc2
+
+# CHECK: llch %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0xc2
+
+# CHECK: llch %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0xc2
+
+# CHECK: llch %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0xc2
+
+# CHECK: llch %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0xc2
+
# CHECK: llgcr %r0, %r15
0xb9 0x84 0x00 0x0f
@@ -3322,6 +3352,36 @@
# CHECK: llh %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x95
+# CHECK: llhh %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0xc6
+
+# CHECK: llhh %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0xc6
+
+# CHECK: llhh %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0xc6
+
+# CHECK: llhh %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0xc6
+
+# CHECK: llhh %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0xc6
+
+# CHECK: llhh %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0xc6
+
+# CHECK: llhh %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0xc6
+
+# CHECK: llhh %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0xc6
+
+# CHECK: llhh %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0xc6
+
+# CHECK: llhh %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0xc6
+
# CHECK: llihf %r0, 0
0xc0 0x0e 0x00 0x00 0x00 0x00
Modified: llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-z196.s?rev=191742&r1=191741&r2=191742&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-z196.s Tue Oct 1 07:19:08 2013
@@ -97,6 +97,22 @@
lhh %r0, 524288
#CHECK: error: invalid operand
+#CHECK: llch %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: llch %r0, 524288
+
+ llch %r0, -524289
+ llch %r0, 524288
+
+#CHECK: error: invalid operand
+#CHECK: llhh %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: llhh %r0, 524288
+
+ llhh %r0, -524289
+ llhh %r0, 524288
+
+#CHECK: error: invalid operand
#CHECK: loc %r0,0,-1
#CHECK: error: invalid operand
#CHECK: loc %r0,0,16
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=191742&r1=191741&r2=191742&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Tue Oct 1 07:19:08 2013
@@ -1611,6 +1611,11 @@
llc %r0, -524289
llc %r0, 524288
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: llch %r0, 0
+
+ llch %r0, 0
+
#CHECK: error: invalid operand
#CHECK: llgc %r0, -524289
#CHECK: error: invalid operand
@@ -1671,6 +1676,11 @@
llh %r0, -524289
llh %r0, 524288
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: llhh %r0, 0
+
+ llhh %r0, 0
+
#CHECK: error: offset out of range
#CHECK: llhrl %r0, -0x1000000002
#CHECK: error: offset out of range
Modified: llvm/trunk/test/MC/SystemZ/insn-good-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-z196.s?rev=191742&r1=191741&r2=191742&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-z196.s Tue Oct 1 07:19:08 2013
@@ -229,6 +229,50 @@
lhh %r0, 524287(%r15,%r1)
lhh %r15, 0
+#CHECK: llch %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xc2]
+#CHECK: llch %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xc2]
+#CHECK: llch %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xc2]
+#CHECK: llch %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0xc2]
+#CHECK: llch %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0xc2]
+#CHECK: llch %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0xc2]
+#CHECK: llch %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0xc2]
+#CHECK: llch %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0xc2]
+#CHECK: llch %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0xc2]
+#CHECK: llch %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0xc2]
+
+ llch %r0, -524288
+ llch %r0, -1
+ llch %r0, 0
+ llch %r0, 1
+ llch %r0, 524287
+ llch %r0, 0(%r1)
+ llch %r0, 0(%r15)
+ llch %r0, 524287(%r1,%r15)
+ llch %r0, 524287(%r15,%r1)
+ llch %r15, 0
+
+#CHECK: llhh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xc6]
+#CHECK: llhh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xc6]
+#CHECK: llhh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xc6]
+#CHECK: llhh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0xc6]
+#CHECK: llhh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0xc6]
+#CHECK: llhh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0xc6]
+#CHECK: llhh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0xc6]
+#CHECK: llhh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0xc6]
+#CHECK: llhh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0xc6]
+#CHECK: llhh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0xc6]
+
+ llhh %r0, -524288
+ llhh %r0, -1
+ llhh %r0, 0
+ llhh %r0, 1
+ llhh %r0, 524287
+ llhh %r0, 0(%r1)
+ llhh %r0, 0(%r15)
+ llhh %r0, 524287(%r1,%r15)
+ llhh %r0, 524287(%r15,%r1)
+ llhh %r15, 0
+
#CHECK: loc %r0, 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xf2]
#CHECK: loc %r0, 0, 15 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xf2]
#CHECK: loc %r0, -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0xf2]
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